Memory Controller Bank Interleaving and Data Reordering
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Solution Overview
Problem
Efficient bank switching during read operations in solid state drives (SSDs) with NAND flash memory is challenging due to the short data read time and the need to maintain data transfer order according to logical addresses, which affects data transfer efficiency and performance.
Innovation Solution
A memory system with multiple nonvolatile semiconductor memories performing bank interleaving, where a controller generates page read commands, allocates them to respective queues, and manages data transfer to coincide with the order of logical addresses specified by read requests, using an automatic transfer manager and read instruction queue manager to optimize data transfer order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bank switching is performed during read operations in NAND flash memory, then data transfer efficiency is improved, but maintaining data transfer order according to logical addresses becomes difficult
Solution Approach 1:
The patent segments the data transfer process into two independent parts: (1) parallel read operations across multiple banks using bank switching, and (2) sequential reordering of read data according to logical addresses. The read management unit handles bank switching while the transfer management unit handles reordering, allowing both efficiency and correctness to be maintained through functional segmentation.
Solution Approach 2:
The patent introduces a transfer management unit as an intermediary between the read management unit and the data transfer process. This intermediary receives read data from multiple banks, reorders it according to logical addresses, and then transfers it sequentially. The intermediary resolves the conflict between parallel read efficiency and sequential transfer requirements.
2Speed
If data is read quickly from NAND flash memory, then read speed is improved, but data must be rearranged to match logical address order, increasing memory area requirements
Solution Approach 1:
The patent extracts the data reordering function from the memory array itself and places it in the transfer management unit. Instead of using additional memory area to store and rearrange data, the system processes and reorders data as it is being transferred from the memory banks to the output interface, eliminating the need for large rearrangement memory.
Solution Approach 2:
The patent changes the dimension of the reordering operation from spatial (using additional memory area) to temporal (reordering during transfer). By performing reordering in the time dimension during the data transfer process rather than in the space dimension using additional memory, the system achieves fast reading without requiring large memory areas for rearrangement.
3Productivity
If bank interleaving is used for parallel read operations, then data transfer speed is improved, but the overhead for managing multiple queues increases
Solution Approach 1:
The patent merges the queue management functions into a unified transfer management unit that handles multiple bank queues. Instead of having separate management overhead for each bank, the transfer management unit consolidates queue management, data reception, and reordering operations into a single integrated controller, reducing the total overhead for managing multiple queues while maintaining parallel read speed.
Data Source
AI summary
Created is transfer order information indicating an order of transfer from multiple memory areas in accordance with an order of logical addresses and memory locations which are specified by read commands. Readout from the multiple memory areas in accordance with the transfer order information is performed by controlling memory controllers in accordance with the created transfer order information.