Memory Controller Write-to-Read Turnaround Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in managing different bank set write-to-read turnaround times, leading to suboptimal performance due to difficulties in arbitrating between same and different bank set read operations, resulting in degraded system performance and bus conflicts.
Innovation Solution
A method and apparatus that utilize operation counter logic, selection logic, acceptance logic, and command formatting logic to manage same and different bank set write-to-read turnaround times by issuing read operations based on specific timing parameters (tWR and tWR-D), allowing early read operations before write completion for optimal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory system waits to send a different bank set read operation based on the same bank set write-to-read turnaround time, then system performance is degraded, but bus conflicts arise if a same bank set read operation is sent based on the different bank set write-to-read turnaround time
Solution Approach 1:
The patent segments the turnaround time management into two separate counters: one for same bank set read operations and another for different bank set read operations. Each counter tracks its specific timing parameter independently, allowing the memory controller to manage each read operation type according to its appropriate timing requirement without interference from the other.
Solution Approach 2:
The patent implements dynamic selection logic that adapts the read operation timing based on the current state of write operations and bank set availability. The system dynamically switches between using tWR and tWR-D timing parameters depending on which bank set is being accessed and whether early read after write is applicable, optimizing performance while preventing bus conflicts.
2Productivity
If early read operations are issued before write completion to different bank sets, then memory system performance is optimized, but timing parameter management becomes complex
Solution Approach 1:
The patent divides the timing management into separate counters for same bank set and different bank set operations. This segmentation simplifies the overall complexity by allowing each counter to independently track its specific timing parameter (tWR or tWR-D) without requiring complex interdependencies between the two timing modes.
Solution Approach 2:
The patent introduces an intermediary selection logic that mediates between the two different timing parameters and the read operation issuance. This selection logic determines which timing parameter applies based on the current bank set state and write operation status, simplifying the management complexity by providing a centralized decision-making mechanism rather than requiring distributed timing management throughout the system.
Data Source
AI summary
A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.