Memory Controller Batch Tag Comparison for NVM Latency
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Solution Overview
Problem
In hybrid memory architectures, the lower access rate of non-volatile memory (NVM) compared to dynamic random access memory (DRAM) leads to increased latency and inefficiency, as NVM is often used as main memory and DRAM as cache, requiring serial processing and frequent tag updates in DRAM, which prolongs memory access times.
Innovation Solution
A memory access method that groups multiple access requests with the same cache line mapping relationship to compare tags centrally, reducing the number of times the cache line tag is read from DRAM, and updates cache line information only when necessary, thereby improving access efficiency and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If DRAM is used as cache for NVM with traditional per-request tag comparison, then cache hit rate is maintained, but memory access latency increases due to frequent tag reads
Solution Approach 1:
The patent merges multiple tag comparison operations into a single batched comparison. Instead of comparing tags for each access request individually, the memory controller groups multiple requests and performs centralized tag comparison by reading the cache line tag once and comparing it against multiple request tags simultaneously. This reduces the frequency of tag reads from DRAM, thereby reducing memory access latency while maintaining cache hit rate.
Solution Approach 2:
The patent implements preliminary action by pre-reading the cache line tag from DRAM before processing multiple access requests. The memory controller retrieves the tag information in advance, stores it temporarily, and then uses it for batched comparison against multiple incoming requests. This preliminary retrieval eliminates the need for repeated tag reads during request processing, reducing overall access latency.
2Reliability
If cache line information is updated for every access request, then cache consistency is maintained, but update overhead increases and access efficiency decreases
Solution Approach 1:
The patent applies partial action by updating cache line information selectively rather than for every access request. The memory controller determines whether an update is necessary based on the access pattern and cache state, performing updates only when required to maintain consistency. This reduces update overhead and improves access efficiency while preserving the necessary cache consistency for reliable operation.
Data Source
AI summary
A memory access technology applied to a computer system includes a first-level memory, a second-level memory, and a memory controller. The first-level memory is configured to cache data in the second-level memory. A plurality of access requests for accessing different memory blocks has a mapping relationship with a first cache line in the first-level memory, and the memory controller compares tags of the plurality of access requests with a tag of the first cache line in a centralized manner to determine whether the plurality of access requests hit the first-level memory.