Memory Controller BCH Matrix Layout for Balanced Block Lengths
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Solution Overview
Problem
There is a need for a systematic design scheme to minimize length differences of respective constituent codes and size differences of respective blocks in symmetric block-wise concatenated Bose-Chaudhuri-Hocquenghem (SBC-BCH) codes to improve decoding performance and reliability in semiconductor memory systems.
Innovation Solution
A controller is designed to generate a square message matrix with an upper triangular matrix and a lower triangular matrix, where the upper triangular matrix includes β numbers of message blocks of size α+1 and (N-β) numbers of message blocks of size α, with specific relationships between α, β, and N, and zero-padding blocks are used to maintain symmetry, allowing for efficient encoding and decoding operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a symmetric block-wise concatenated BCH code is used to improve error correction capability, then the reliability is improved, but the length differences of constituent codes and size differences of blocks increase, making systematic design difficult
Solution Approach 1:
The message matrix is segmented into multiple blocks with different sizes (α and α+1). The patent divides the k×k message matrix into N blocks, where some blocks have size α and others have size α+1. This segmentation allows the system to handle variable block sizes systematically while maintaining the overall symmetric structure required for SBC-BCH coding, thus resolving the design complexity issue while preserving error correction capability.
Solution Approach 2:
Different blocks within the message matrix are assigned different local qualities (sizes). The patent applies local quality by having some message blocks of size α and others of size α+1, with specific blocks selected to have the larger size based on the parameter β. This local variation in block quality enables the systematic design of the message matrix while maintaining the required symmetry and error correction properties.
2Ease of manufacture
If block sizes are made uniform to simplify design, then the ease of manufacture is improved, but the error correction performance deteriorates due to inability to optimize for different code lengths
Solution Approach 1:
The patent changes the parameters of the message matrix blocks systematically. Instead of using uniform block sizes, it introduces two parameter values (α and α+1) and controls their distribution through the parameter β. This parameter change approach allows the system to optimize error correction performance for different code lengths while maintaining a regular, systematic design pattern that is easier to manufacture compared to arbitrary block size variations.
3Reliability
If different sized blocks are used to optimize error correction for varying code lengths, then the error correction capability is improved, but the device complexity increases due to multiple block size management
Solution Approach 1:
The message matrix design achieves universality by creating a systematic framework that can handle multiple block sizes (α and α+1) through a unified structure. The patent defines a universal design pattern where β blocks have size α+1 and (N-β) blocks have size α, arranged in a symmetric configuration. This universal approach allows the same design methodology to be applied regardless of the specific values of α, β, or N, reducing the perceived complexity while maintaining optimized error correction capability.
Data Source
AI summary
An operating method of a controller includes generating a square message matrix of k×k; and generating an encoded message by encoding the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code, wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix, wherein the upper triangular matrix includes “β” numbers of message blocks, each of which has a size of “α+1”, and “(N−β)” numbers of message blocks, each of which has a size of “α”, and wherein “α”, “β” and N have relationships represented by equations 1 and 2:α=⌊MN⌋[Equation1]β=MmodN[Equation2]where “M” represents a size of a message input from a host and “N” represents a number of message blocks forming the upper triangular matrix.