Memory Controller with Shared BCH Parity Circuits for Fast Error Correction
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently correcting errors, particularly random, burst, and mixed errors, as increasing error correction code bits enlarges circuit size and reduces processing speed, and conventional error correction codes require iterative decoding processes that are complex and time-consuming.
Innovation Solution
A memory controller employing a two-dimensional product-code system using BCH codes, where data is encoded in both row and column directions with shared parity generation circuits, enabling fast encoding and decoding by alternating iterative processes between row and column directions, reducing circuit size and processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of bits of the error correction code is increased to improve correction ability, then the correction ability is improved, but the circuit size increases and processing speed decreases
Solution Approach 1:
The patent applies segmentation by dividing the error correction code into two separate codes (C1 and C2) with different correction capabilities. Code C1 is optimized for random errors while code C2 handles burst errors. This segmentation allows each code to be designed with appropriate bit lengths for its specific error type, avoiding the need for a single overly complex code that would correct all error types equally, thus reducing overall circuit size while maintaining comprehensive error correction ability.
Solution Approach 2:
The patent implements a two-dimensional product code structure where data is arranged in a matrix and encoded in both row and column directions. This dimensional approach allows errors to be corrected by utilizing redundancy from both dimensions. The row codes (C1) and column codes (C2) work together to correct errors that a single-dimensional code could not handle, improving correction ability without requiring excessive bits in a single code dimension.
2Reliability
If the number of bits of the error correction code is increased to improve correction ability, then the correction ability is improved, but the processing speed decreases
Solution Approach 1:
By segmenting the error correction into two separate coding passes (row direction with code C1, then column direction with code C2), the patent enables parallel processing of different data segments. Each code can be processed independently in its respective dimension, improving processing throughput compared to a single monolithic code that would require sequential processing of all bits.
Solution Approach 2:
The two-dimensional product code structure enables simultaneous encoding and decoding operations in both row and column dimensions. This dimensional parallelism allows the system to process multiple data blocks concurrently, significantly improving processing speed while maintaining strong error correction capabilities through the combined redundancy of both dimensions.
3Reliability
If conventional error correction codes are used to handle various error types, then comprehensive error correction is achieved, but the decoding process becomes complex and time-consuming
Solution Approach 1:
The patent segments the decoding process into two distinct stages: first decoding row codes (C1) to correct random errors, then decoding column codes (C2) to correct burst errors. This segmentation simplifies each individual decoding step compared to a single complex universal decoder, as each code can be optimized for its specific error type. The modular structure reduces decoding complexity while maintaining the ability to handle mixed error types.
Solution Approach 2:
By introducing the column dimension as a second coding layer, the patent creates a product code structure where row and column decoders work independently in their respective dimensions. This dimensional separation allows each decoder to be simpler and more specialized, rather than requiring a single complex decoder to handle all error patterns. The intersection of row and column codes provides redundant information that simplifies the error detection and correction logic in each dimension.
Data Source
AI summary
A memory controller is a memory controller including an encoder that product-codes, with a linear code, data to be recorded in a memory section and a decoder that decodes product-coded data read out from the memory section. The encoder and the decoder share a parity generation circuit including a plurality of remainder calculating and retaining sections, each including a remainder calculation circuit by a generator polynomial and a retaining circuit that retains an output of the remainder calculation circuit.