Memory Controller Binary Code Substitution for NAND Flash
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Solution Overview
Problem
As the capacity of NAND Flash increases, the complexity of operations in multi-bit storage systems, such as those using TLC, QLC, and PLC memory cells, leads to longer programming durations, reduced data retention, and increased disturbance suppression challenges.
Innovation Solution
The memory controller implements a method to substitute binary codes in input data with replacement binary codes corresponding to preset replacement programming levels, thereby reducing the number of states in threshold voltage distributions and improving data retention and disturbance suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit storage is implemented to increase capacity, then storage density is improved, but programming duration is extended and operation complexity increases
Solution Approach 1:
The patent segments the programming operation into multiple stages with different programming levels. Each stage targets specific threshold voltage ranges, allowing progressive programming of memory cells. This segmentation enables efficient multi-bit storage by dividing the complex programming task into manageable steps, reducing overall programming duration while maintaining high storage capacity.
Solution Approach 2:
The patent changes the programming parameters by selecting different programming levels corresponding to different threshold voltage ranges. By dynamically adjusting programming parameters based on the target storage capacity and memory cell state, the system optimizes programming efficiency. This parameter change approach allows the same hardware to efficiently handle various storage requirements without increasing programming duration.
2Quantity of substance
If multi-bit storage is implemented to increase capacity, then storage density is improved, but data retention is reduced
Solution Approach 1:
The patent performs preliminary actions by pre-establishing threshold voltage ranges and programming levels before actual programming operations. This preliminary configuration allows the system to optimize programming parameters in advance, ensuring that data is written into stable threshold voltage states that guarantee long-term retention. The preliminary setup enables reliable data storage even at higher capacities.
Solution Approach 2:
The patent implements feedback mechanisms to monitor and verify programming results. By checking the threshold voltage of programmed memory cells and adjusting subsequent programming operations accordingly, the system ensures data retention reliability. This feedback loop allows correction of programming errors and optimization of retention characteristics, maintaining high reliability even as storage capacity increases.
3Quantity of substance
If multi-bit storage is implemented to increase capacity, then storage density is improved, but disturbance suppression becomes more difficult
Solution Approach 1:
The patent applies local quality by targeting specific local regions in the threshold voltage distribution for programming. Each programming level corresponds to a specific local region (threshold voltage range), allowing precise programming without affecting other regions. This localized approach reduces cross-talk and disturbance between adjacent memory cells, enabling high-capacity storage while maintaining strong disturbance suppression.
Solution Approach 2:
The patent segments the threshold voltage distribution into distinct regions, each corresponding to a specific programming level. By programming memory cells into distinct, well-separated threshold voltage regions, the system minimizes overlap and disturbance between different data states. This segmentation of the voltage space allows high-density storage while maintaining clear distinction between states, thereby suppressing disturbance.
Data Source
AI summary
Memory controllers, memory devices, memory systems and operation methods are provided. A memory controller is to: find, in input data, a binary code to be replaced corresponding to a preset programming level to be replaced, the input data is to be written into a memory cell; and substitute the binary code to be replaced in the input data with a replacement binary code corresponding to a preset replacement programming level, and generate a replacement identifier linking a memory address corresponding to the replacement binary code. The quantity of states is reduced by modifying a data encoding mode of the memory controller to help shorten programming duration of the memory device and reduce disturbance.