Memory Controller BIST with Command Scheduler and Switch

Solution Overview

Problem

The increasing integration of memory systems leads to higher costs and times for testing, with existing fault detection algorithms being either inefficiently short or excessively long, and built-in self-testers becoming redundant and increasing chip size when embedded.

Innovation Solution

A memory controller with a built-in self-tester, scheduler, and main controller that allows real-time testing by reconfiguring command execution orders and using a switch to direct test commands, enabling direct user input and shared control for efficient memory operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a BIST is embedded into a semiconductor chip, then the test cost decreases, but the size of the semiconductor chip increases

Engineering Contradiction:

Improvetest costVSAvoidchip size

Core Design Contradiction:

Ease of manufactureVSVolume of moving object

Solution Approach 1:

The patent merges the BIST functionality with the main controller by using the main controller's existing command generation and control capabilities to execute test operations. The switch enables the main controller to receive either normal commands from the scheduler or test commands from the BIST, combining testing functionality with the existing control architecture without requiring a separate dedicated BIST controller, thereby reducing overall chip area while maintaining test capability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The main controller is designed to serve dual purposes: it functions as the primary controller for normal memory operations and as the controller for BIST operations. The switch mechanism allows the main controller to selectively process commands from either the scheduler (for normal operations) or the BIST (for testing), making the main controller universal and eliminating the need for a separate BIST controller, thus reducing chip size while maintaining test functionality

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Ease of manufacture

If a BIST or BIT is embedded into a semiconductor chip, then the test cost decreases, but the BIST or BIT becomes redundant after the test

Engineering Contradiction:

Improvetest costVSAvoidpost-test utility

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The main controller serves dual purposes: it functions as the primary controller for normal memory operations and as the controller for BIST operations. The switch mechanism allows the main controller to selectively process commands from either the scheduler (for normal operations) or the BIST (for testing), making the main controller universal and eliminating the need for a separate BIST controller, thus reducing chip size while maintaining test functionality

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the BIST functionality with the main controller by using the main controller's existing command generation and control capabilities to execute test operations. The switch enables the main controller to receive either normal commands from the scheduler or test commands from the BIST, combining testing functionality with the existing control architecture without requiring a separate dedicated BIST controller, thereby reducing overall chip area while maintaining test capability

Inventive Principle:

Principle #5Merging (Combining)

3Loss of time

If march test algorithm is used, then the test time is short, but the fault detection accuracy is low

Engineering Contradiction:

Improvetest timeVSAvoidfault detection accuracy

Core Design Contradiction:

Loss of timeVSMeasurement precision

Solution Approach 1:

The patent implements a dynamic test approach where the test algorithm can be selected and configured based on requirements. The BIST can execute different test algorithms (march test, non-march test, or custom algorithms) by loading different test patterns and control logic into its memory and control unit, allowing the system to adaptively choose between speed and accuracy depending on the specific testing needs

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The BIST architecture allows changing test parameters such as test algorithm type, test patterns, memory regions to be tested, and test depth. By modifying these parameters, the system can switch between quick march tests for routine checking and more comprehensive non-march tests for detailed fault detection, optimizing the balance between test time and accuracy for different scenarios

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11392313B2Memory controller and method thereof with built-in self-tester (BIST)

Publication Date: 2022.07.19 SILICON WORKS CO LTD

AI summary

A memory controller according to an aspect of the present invention includes a BIST (built-in self-tester) configured to test a memory, a scheduler configured to change an execution order of memory commands to be transmitted to the memory, a main controller configured to control the memory, and a switch configured to connect one of an output of the scheduler and an output of the BIST to an input of the main controller in response to a control signal output from the BIST.