Memory Controller Permanent Bit Error Handling
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Solution Overview
Problem
Existing memory systems face challenges in handling permanent bit errors, particularly in high-radiation environments, where recycling power is necessary to correct single event latchup (SEL) errors, leading to system downtime and increased costs due to the need for specialized circuitry and more expensive radiation-insulated memory devices.
Innovation Solution
A memory system with a primary and secondary storage partition, along with a memory controller that detects and corrects bit errors using an error detection and correction (EDAC) circuit, flags permanent errors, and redirects subsequent operations to the secondary partition, eliminating the need for power recycling by distinguishing between non-permanent and permanent errors based on previous access history.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power recycling is used to correct single event latchup (SEL) errors, then permanent bit errors can be corrected, but system downtime occurs and specialized circuitry is required
Solution Approach 1:
The memory device is divided into multiple banks, allowing the system to continue operating with unaffected banks while one bank undergoes correction or replacement, thereby eliminating system downtime associated with error correction
Solution Approach 2:
The patent implements a replacement mechanism where affected memory banks are replaced with spare banks, copying the functional capability without requiring power recycling or causing system downtime
2Reliability
If radiation-insulated memory devices are used to prevent permanent bit errors, then reliability in high-radiation environments is improved, but cost increases
Solution Approach 1:
The patent uses standard, cost-effective memory devices with built-in error detection and correction capabilities, replacing them when permanent errors occur rather than using expensive radiation-insulated memory devices
Solution Approach 2:
The memory controller automatically detects errors, identifies affected banks, and performs replacement operations without external intervention, maintaining reliability while using standard components
3Reliability
If specialized circuitry is added to power supply to enable power recycling, then permanent bit errors can be corrected, but device complexity increases
Solution Approach 1:
The patent extracts the error correction function from the power supply circuitry and relocates it to the memory controller, which uses error detection codes to identify and handle permanent errors without requiring specialized power recycling circuitry
Solution Approach 2:
The patent replaces the mechanical/power-based error correction method (power recycling) with a control-based method using error detection and correction codes, eliminating the need for specialized power supply circuitry
Data Source
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AI summary
A memory system (10) including a primary memory storage partition (17), a secondary memory storage partition (18), and a memory controller (14) that is connected to read and write to the primary memory storage partition (17) and detects a permanent bit error at an address associated with the primary memory storage partition (17). In response to a detected permanent bit error, the memory controller (14) stores data from the address associated with the permanent bit error to an address associated with the secondary memory storage partition (18).