Memory Controller Wear Leveling via Bit Error Rate Sorting

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Solution Overview

Problem

Conventional wear leveling techniques in rewritable non-volatile memory modules prematurely label physical erasing units as defective based solely on usage counts, leading to shortened lifespan, as they do not account for varying bit error rates across units.

Innovation Solution

A memory management method that groups physical erasing units into a spare and data area, sorting them by erasing count or bit error rates to select the most suitable units for data writing, thereby extending the lifespan of the module.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If physical erasing units are labeled as defective based solely on usage counts reaching the limit, then the wear leveling technique can be implemented simply, but the lifespan of the memory module is shortened

Engineering Contradiction:

Improvewear leveling implementation complexityVSAvoidmemory module lifespan

Core Design Contradiction:

Device complexityVSDuration of action of stationary object

Solution Approach 1:

The patent changes the parameter for evaluating physical erasing units from solely 'usage count' to a composite parameter that includes both 'usage count' and 'bit error rate'. This allows units with high usage counts but low bit error rates to be retained and reused, thereby extending memory module lifespan without significantly increasing implementation complexity

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent introduces feedback through continuous monitoring of bit error rates in physical erasing units. By feeding back the bit error rate information to the memory management circuit, the system can dynamically adjust which units are considered defective, preventing premature disposal of units that remain functional despite high usage counts

Inventive Principle:

Principle #23Feedback

2Reliability

If physical erasing units with high bit error rates are discarded, then data reliability is maintained, but the lifespan of the memory module is reduced

Engineering Contradiction:

Improvedata reliabilityVSAvoidmemory module lifespan

Core Design Contradiction:

ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent applies local quality by differentiating the evaluation criteria for different physical erasing units based on their individual bit error rates. Units with low bit error rates are retained even if they have high usage counts, while units with high bit error rates are discarded. This localized differentiation allows maximum utilization of reliable units without compromising data integrity

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the decision parameter from binary 'usage count threshold' to a nuanced evaluation that incorporates both 'usage count' and 'bit error rate'. This parameter change enables the system to distinguish between units that are merely worn versus units that are actually defective, extending lifespan while maintaining reliability

Inventive Principle:

Principle #35Parameter changes

3Ease of operation

If conventional wear leveling is used without considering bit error rates, then the management process is simple, but the lifespan of the memory module is shortened

Engineering Contradiction:

Improvememory management easeVSAvoidmemory module lifespan

Core Design Contradiction:

Ease of operationVSDuration of action of stationary object

Solution Approach 1:

The patent implements self-service by having the memory management circuit automatically monitor and evaluate bit error rates in physical erasing units without external intervention. The system self-adjusts its wear leveling strategy based on real-time error rate data, maintaining ease of operation while extending memory module lifespan through intelligent unit selection

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS9236148B2Memory management method, memory control circuit unit and memory storage apparatus

Publication Date: 2016.01.12 PHISON ELECTRONICS

AI summary

A memory management method, a memory control circuit unit using the method, and a memory storage apparatus using the method are provided. The memory management method includes determining whether a use count of the rewritable non-volatile memory module is greater than a use count threshold; based on a result of the determination, sorting each physical erasing unit in a spare area in an ascending manner according to an erasing count of each physical erasing unit in the spare area or according to the number of maximum bit errors of the physical erasing units in the spare area, so as to form a plurality of sorted physical erasing units; and selecting the foremost physical erasing unit from the spare area to write data according to the sorted physical erasing units. By applying the memory management method, the lifespan of the rewritable non-volatile memory module may be effectively prolonged.