Memory Controller Parity Checking for MLC Bit-Flip Errors
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Solution Overview
Problem
Memory devices with multi-level cell (MLC) flash memory face instability issues due to bit flipping caused by external factors, leading to potential system crashes, and existing management mechanisms are inadequate in preventing such errors without increasing costs or causing side effects.
Innovation Solution
A method for data processing in memory devices that involves encoding data to generate a parity-check code, writing the codeword into volatile memory, and determining its correctness upon readout, with error information stored if the data is incorrect, using a controller with a processing circuit, volatile memory, encoding and decoding circuits, and a register to manage operations and handle errors effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC flash memory is used to increase storage capacity and reduce cost, then storage density and cost-effectiveness are improved, but data stability and reliability deteriorate due to bit flipping
Solution Approach 1:
The patent applies preliminary action by encoding data with parity-check codes before writing to volatile memory. The encoding circuit generates parity-check codes in advance and stores them together with the original data in the volatile memory, so that when bit flipping occurs, the error can be detected and corrected using the pre-stored parity information, thus preventing system crashes.
Solution Approach 2:
The patent introduces an intermediary mechanism by adding an encoding circuit and parity-check code system between the data source and the volatile memory. This intermediary layer processes the data by adding redundant parity information, which acts as a mediator to detect and correct errors caused by bit flipping, thereby improving reliability without sacrificing storage capacity.
2Reliability
If parity-check coding is implemented to detect and correct bit flipping errors, then data reliability is improved, but device complexity and processing overhead increase
Solution Approach 1:
The patent applies local quality by implementing error detection and correction only in the volatile memory portion of the controller, not throughout the entire memory system. The encoding circuit is specifically placed in the controller to protect data in volatile memory, while the non-volatile flash memory maintains its original structure. This localized approach improves reliability where needed without unnecessarily complicating the entire system.
Data Source
AI summary
A method for performing data processing for error handling in a memory device, the memory device and the controller thereof, and the associated electronic device are provided. The method may include: programming a codeword of a set of data into a non-volatile (NV) memory, wherein the codeword includes the set of data and a parity-check code; reading the codeword from a volatile memory to generate readout data of the codeword; determining whether the readout data is correct according to the readout version of the set of data and the readout version of the parity-check code; and when determining that the readout data is correct, outputting the readout version of the set of data as the set of data for further usage of the processing circuit, otherwise, sending a predetermined signal to the processing circuit and storing error information regarding the set of data into a register of the controller.