Memory Controller Wear Leveling via Bit Order Reversal
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Solution Overview
Problem
Non-volatile memory systems face challenges in extending the durability and lifetime of memory cells due to uneven wear and tear, particularly during write operations, which can lead to premature failure and reduced performance.
Innovation Solution
A memory controller and system that change the bit order of data during write operations and restore it during read operations, using a memory controller to manage state information and perform read-modify-write operations to distribute wear evenly across memory cells, thereby leveling wear and extending the lifespan of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written to non-volatile memory chips without bit order changes, then write operations are simple and fast, but wear is concentrated on specific memory cells leading to reduced durability
Solution Approach 1:
The patent applies preliminary action by changing the bit order of data before writing to memory chips. The memory controller performs bit order changes on write data based on wear state information before the actual write operation, thereby distributing wear evenly across memory cells in advance and preventing concentration of wear on specific cells.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the bit order of data based on the wear state of memory chips. The memory controller changes parameters such as bit arrangement patterns and write destination selection according to real-time wear information, thereby optimizing wear distribution across different memory cells.
2Reliability
If wear-leveling processes are performed frequently to distribute wear evenly, then durability of memory cells is improved, but system performance and efficiency are reduced
Solution Approach 1:
The patent applies continuity of useful action by integrating bit order changes into every normal write operation rather than performing separate wear-leveling processes. The memory controller continuously distributes wear during routine data writes by adjusting bit orders, thereby achieving wear-leveling as a byproduct of normal operations without additional performance overhead.
Solution Approach 2:
The patent applies self-service by enabling the memory controller to automatically adjust bit orders based on stored wear state information without requiring external wear-leveling commands. The system serves itself by using wear information to autonomously optimize write operations and distribute wear evenly across memory cells.
3Duration of action of stationary object
If bit order is changed during write operations to distribute wear, then durability is extended, but additional processing time and complexity are required
Solution Approach 1:
The patent applies partial or excessive action by selectively changing bit orders only when wear distribution is needed, rather than always performing full bit order changes. The memory controller uses wear state information to determine when bit order changes are necessary, thereby reducing unnecessary processing while still achieving effective wear distribution.
Data Source
AI summary
According to one embodiment, a memory controller controls a plurality of non-volatile memory chips. The memory controller includes a memory that stores first data and a processing unit that processes the first data stored in the memory. During a write operation, the processing unit generates second data including the first data and additional data corresponding to the first data, changes the bit order of the second data based on information indicating the state of the write destination of the second data, and writes the second data having the changed bit order to the plurality of non-volatile memory chips. During a read operation, the processing unit reads the second data having the changed bit order from the plurality of non-volatile memory chips and revert the bit order of the read second data to the original state based on the information.