Nonvolatile Memory Controller Defective Bit Line Skip Mechanism
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Solution Overview
Problem
Conventional data storage apparatuses in portable electronic devices face challenges in efficiently managing defective bit lines, leading to reduced usable data regions and increased product discard rates due to complex circuitry and byte-by-byte redundancy replacement methods.
Innovation Solution
A data storage apparatus that includes a nonvolatile memory device and a controller capable of detecting and skipping defective bit lines during write and read operations by inserting dummy bits and shifting data, eliminating the need for a separate redundancy region and circuitry for replacement, thereby increasing the number of permissible defective bit lines and reducing product discard rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If byte-by-byte redundancy replacement method is used for defective bit lines, then data reliability is maintained, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent segments the bit line into multiple segments and identifies defective portions, then replaces only the defective segments rather than entire byte units. This segmentation allows for more granular defect management, reducing the overhead of redundancy circuits while maintaining data reliability.
Solution Approach 2:
The patent applies local quality by providing redundancy resources only where defects occur rather than uniformly across the entire memory array. The defect management circuit dynamically allocates redundancy bit lines to specific defective bit line segments, optimizing resource usage and reducing overall device complexity.
2Reliability
If redundancy region is allocated for defective bit line replacement, then data reliability is improved, but usable data region decreases
Solution Approach 1:
The patent implements dynamic defect management where the redundancy allocation is not fixed but adapts based on actual defect locations and patterns. The defect management circuit dynamically maps defective bit line segments to available redundancy resources, allowing the system to handle defects flexibly without pre-allocating large redundancy regions.
Solution Approach 2:
The patent changes the parameter of redundancy allocation from static byte-by-byte replacement to dynamic bit-level segment replacement. By changing how redundancy is allocated and managed, the system achieves the same reliability level with significantly reduced redundancy overhead, increasing the usable data region.
3Reliability
If complex redundancy management circuitry is implemented, then defect handling capability is improved, but manufacturing yield decreases
Solution Approach 1:
The patent implements a defect skip mechanism where the defect management circuit identifies defective bit line segments and skips them during read/write operations by redirecting access to redundancy bit lines. This skipping approach allows the system to handle defects without complex replacement circuitry, simplifying the manufacturing process and improving yield.
Solution Approach 2:
The defect management circuit performs self-service by automatically detecting, managing, and compensating for defects without external intervention. The system autonomously handles defect mapping and redundancy allocation, reducing the need for complex external management circuits and simplifying the overall system architecture for better manufacturability.
Data Source
AI summary
A data storage apparatus includes a nonvolatile memory device and a controller configured to determine whether or not one or more addresses of defective bit lines are included in an address of a write data to be written into the nonvolatile memory device or an address of a read data read from the nonvolatile memory device, and write the write data or read the read data by skipping the defective bit lines based on a determination result.