Memory Controller Core Assignment via Bitmap Segmentation
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Solution Overview
Problem
Conventional memory controllers inefficiently assign logical block addresses to multiple cores, leading to uneven workload distribution and increased operational stress on individual cores, which deteriorates overall memory device performance.
Innovation Solution
A memory controller with multiple cores and a bitmap storage system that assigns logical block addresses based on a predetermined assignment ratio, ensuring even distribution across cores, regardless of whether the addresses are even or odd, thereby optimizing core utilization and reducing operational stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If logical block addresses are assigned to multiple cores using conventional methods, then the memory controller can handle more addresses, but the workload becomes unevenly distributed causing increased operational stress on individual cores
Solution Approach 1:
The patent segments the logical block address assignment process by dividing addresses into even and odd groups, assigning each group to different cores. This segmentation ensures balanced workload distribution across multiple cores, preventing any single core from bearing excessive operational stress while maintaining high address handling capacity.
2Device complexity
If all logical block addresses are assigned to a single core, then the assignment process is simple, but the core experiences concentrated program and erase cycles reducing overall system efficiency
Solution Approach 1:
The patent implements segmentation by separating logical block addresses into even and odd categories, with each category assigned to different cores. This approach maintains relatively simple assignment logic while dramatically improving system efficiency through parallel processing and balanced workload distribution across multiple cores.
Solution Approach 2:
The patent merges the capabilities of multiple cores to handle different segments of logical block addresses simultaneously. By combining the processing power of multiple cores through coordinated even/odd address assignment, the system achieves higher overall efficiency without significantly increasing individual core complexity.
3Ease of operation
If logical block addresses are assigned without considering even/odd patterns, then the assignment is straightforward, but workload concentration occurs on specific cores
Solution Approach 1:
The patent segments addresses based on their even/odd characteristics, creating distinct assignment paths for each parity group. This segmentation maintains operational simplicity by using basic parity checks while achieving balanced workload distribution across cores, preventing any single core from becoming a bottleneck.
Data Source
AI summary
Provided herein may be a memory controller and a method of operating the same. The memory controller for controlling a plurality of memory devices in which data is stored may include a host interface configured to receive a request and a logical address corresponding to the request from a host, a processor including multiple cores, each configured to receive the logical address from the host interface and generate mapping information indicating a mapping relationship between the logical address and a physical address and a bitmap storage configured to store a bitmap indicating which core of the multiple cores each of previously-received logical addresses is assigned, wherein the host interface assigns the logical address to one of the multiple cores based on the bitmap.