Memory Controller Bitmaps for Flush Command Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in maintaining operation speed when a flush command is input, as they often block subsequent commands, leading to interruptions and reduced performance.
Innovation Solution
A memory system comprising a semiconductor memory device and a controller that generates and manages bitmaps to track uncompleted operations, allowing the system to process flush commands without blocking additional commands by using a master bitmap and flush bitmap to ensure seamless operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory system processes a flush command to ensure data completion, then data reliability is improved, but subsequent commands are blocked causing operating speed to deteriorate
Solution Approach 1:
The patent segments the command processing into multiple independent queues: a flush command queue for ensuring data completion and a normal command queue for continuous command processing. This segmentation allows the system to handle flush commands without blocking subsequent normal commands, resolving the contradiction between reliability and speed by enabling parallel processing of different command types.
Solution Approach 2:
The patent implements preliminary action by pre-allocating separate command queues and establishing clear processing priorities before conflicts occur. The flush command queue is prepared in advance to handle completion assurance tasks, while the normal command queue is ready to continue processing without interruption. This preliminary structuring prevents blocking issues and maintains high operating speed while ensuring data reliability.
2Reliability
If the memory system blocks subsequent commands during flush command processing to ensure data integrity, then data reliability is improved, but productivity deteriorates due to reduced command throughput
Solution Approach 1:
The patent divides the command processing system into segmented queues that operate independently. The flush command queue handles integrity-assurance commands while the normal command queue maintains high throughput for regular operations. This segmentation eliminates the need to block subsequent commands during flush processing, thereby maintaining both data integrity and high command throughput.
Solution Approach 2:
The patent ensures continuity of useful action by allowing the normal command queue to continue processing commands without interruption even when flush commands are being executed. This continuous processing maintains high productivity and command throughput while the flush queue separately handles integrity assurance, preventing any pause in overall system productivity.
3Device complexity
If the memory system uses a single command queue for all commands, then device complexity is reduced, but operating speed deteriorates due to command blocking
Solution Approach 1:
The patent applies segmentation by dividing the single command queue into multiple specialized queues (flush command queue and normal command queue). Although this increases structural complexity slightly, it dramatically improves operating speed by eliminating command blocking. The segmented structure allows parallel processing of different command types, resolving the contradiction between simplicity and speed.
Solution Approach 2:
The patent implements dynamic command routing that directs different command types to appropriate queues based on their nature. This dynamic approach optimizes processing efficiency by ensuring that flush commands and normal commands are handled in their respective queues, preventing unnecessary blocking and improving overall operating speed while maintaining manageable system complexity.
Data Source
AI summary
There are provided a memory system and an operating method thereof. A memory system includes: a semiconductor memory device for including a plurality of semiconductor memories, and operating in response to a plurality of internal commands received thereto; and a controller for generating and queuing the plurality of internal commands in response to a plurality of commands received from a host, and generating and storing a master bitmap including information on unperformed operations that are not performed in the semiconductor memory device for internal commands among the plurality of queued internal commands. The controller generates a flush bitmap corresponding to a flush command, using a current master bitmap, when the flush command is received from the host, and clears the flush bitmap if the semiconductor memory device completes the unperformed operations.