Memory Controller Block Reuse Scheduling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Direct host control of nonvolatile memory in storage devices increases host-side burden and may not achieve sufficient I/O performance, necessitating a reduction in this burden to enhance storage device efficiency.
Innovation Solution
A memory system with a controller that manages nonvolatile memory blocks, including a NAND interface, and executes commands like read, write, and reuse operations, ensuring incomplete read commands are completed before transitioning blocks to a reusable state, thereby reducing host-side processing overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the host directly controls nonvolatile memory in the storage device, then the host can access the storage device, but the host-side burden increases and sufficient I/O performance cannot be obtained
Solution Approach 1:
The patent introduces a storage device with a controller that acts as an intermediary between the host and nonvolatile memory. The controller manages memory blocks, handles read/write/erase commands, and tracks command completion status, thereby reducing the host-side burden while maintaining efficient I/O performance through automated block management and collision prevention mechanisms
2Productivity
If the storage device manages block states and command execution, then I/O performance is enhanced, but device complexity increases
Solution Approach 1:
The patent segments the storage device functionality into distinct modules: a management unit that tracks block states and command status, and a control unit that executes commands. This segmentation allows independent optimization of each module, managing complexity through functional separation while enabling efficient parallel operation of read and reuse/erase commands
3Productivity
If read commands are executed concurrently with reuse/erase commands, then I/O performance improves, but command collisions may occur
Solution Approach 1:
The patent implements a feedback mechanism where the management unit continuously monitors the execution status of read commands and the state of memory blocks. Based on this feedback, the control unit intelligently schedules reuse/erase commands to execute only after relevant read commands are complete, preventing collisions while maintaining high parallel execution efficiency
Data Source
AI summary
According to one embodiment, a memory system receives from a host read commands each designating both of a block address of a read target block and a read target storage location in the read target block, and executes a data read operation in accordance with each of the received read commands. In response to receiving from the host a first command to transition a first block to which data is already written to a reusable state of being reusable as a new write destination block, the memory system determine whether an incomplete read command designating a block address of the first block exists or not. In a case where the incomplete read command exists, the memory system executes the first command after execution of the incomplete read command is completed.