Multi-Mode Memory Controller Block Segmentation
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Solution Overview
Problem
The increasing demand for higher capacity and lower cost memory systems using NAND flash memory leads to finer processes and three-dimensional memory cell placement, but this results in deterioration of the maximum number of program/erase cycles and write performance.
Innovation Solution
A memory system with a controller that manages multiple storage modes (SLC, MLC, TLC, QLC) by assigning blocks to different areas and using a buffer area to optimize data transcription and storage, thereby extending the memory system's lifetime and maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-levelled recording method is adopted to increase capacity and reduce cost, then storage capacity increases and cost decreases, but write performance and maximum number of P/E cycles deteriorate
Solution Approach 1:
The memory device is divided into multiple memory blocks, each capable of operating in different recording modes (SLC, MLC, TLC, QLC). This segmentation allows the system to optimize write performance by using SLC mode for performance-critical operations while maintaining high capacity through QLC mode for bulk storage, thus resolving the contradiction between capacity and write performance.
Solution Approach 2:
The memory device dynamically switches between different recording modes (SLC, MLC, TLC, QLC) based on operational requirements. The controller can adjust the recording mode for each memory block independently, enabling the system to adapt write performance and capacity characteristics in real-time, thereby balancing the trade-off between write speed and storage density.
2Quantity of substance
If multi-levelled recording method is adopted to increase capacity and reduce cost, then storage capacity increases and cost decreases, but maximum number of P/E cycles deteriorates
Solution Approach 1:
The memory device is divided into multiple memory blocks, each capable of operating in different recording modes (SLC, MLC, TLC, QLC). This segmentation allows the system to optimize write performance by using SLC mode for performance-critical operations while maintaining high capacity through QLC mode for bulk storage, thus resolving the contradiction between capacity and write performance.
Solution Approach 2:
The memory device dynamically switches between different recording modes (SLC, MLC, TLC, QLC) based on operational requirements. The controller can adjust the recording mode for each memory block independently, enabling the system to adapt write performance and capacity characteristics in real-time, thereby balancing the trade-off between write speed and storage density.
3Quantity of substance
If data is written in second mode (more bits per cell) to increase capacity, then storage capacity increases, but write performance deteriorates
Solution Approach 1:
The memory device is divided into multiple memory blocks, each capable of operating in different recording modes (SLC, MLC, TLC, QLC). This segmentation allows the system to optimize write performance by using SLC mode for performance-critical operations while maintaining high capacity through QLC mode for bulk storage, thus resolving the contradiction between capacity and write performance.
Solution Approach 2:
Different memory blocks are assigned different recording modes based on local requirements. Performance-critical data can be written to blocks operating in SLC mode with higher write speeds, while capacity-critical data can be written to blocks in QLC mode with higher density. This local quality differentiation resolves the contradiction between write speed and storage capacity.
Data Source
AI summary
A controller assigns a first plurality of blocks among a plurality of blocks provided in a non-volatile memory to a first area, assigns a second plurality of blocks to a second area, and assigns a third plurality of blocks to a third area. The controller uses each block assigned to the first area in a first mode, uses each block assigned to the second area in a second mode in which the number of bits of data written in each memory cell is larger than that in the first mode, and uses each block assigned to the third area in the first mode or the second mode. The controller writes data received from a host device to an area that corresponds to a designation from the host device out of the first area and the third area. The controller transcribes valid data written to the first area and the third area to the second area.