Memory Controller Block Sorting for Multi-Memory Utilization
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Solution Overview
Problem
Existing memory controllers underutilize multiple memories when the data transfer rate between the host and the memory controller exceeds the rate between the controller and a single memory, leading to decreased system access performance.
Innovation Solution
A method and memory controller that sorts blocks of multiple memories in a non-sequential successive order to ensure equal access to both memories, allowing simultaneous access and increasing utilization and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory controller sequentially accesses blocks from multiple memories, then the access process is simple, but the utilization rate of memories decreases and access performance is reduced
Solution Approach 1:
The memory controller performs preliminary sorting of blocks from multiple memories before actual data access. By pre-organizing blocks in a non-sequential successive order and mapping them to sequential disk logical addresses, the system prepares the memory structure in advance to enable simultaneous access during operation, thereby improving memory utilization rate without complicating the actual access process
Solution Approach 2:
The patent segments the memory access process into two independent parts: (1) block sorting and address mapping, which is performed in advance; and (2) actual data access, which can proceed simultaneously. This segmentation allows the complex sorting operation to be separated from the access operation, enabling simple sequential access from the host's perspective while achieving simultaneous memory access underneath
2Productivity
If the memory controller sequentially accesses blocks from multiple memories, then the control logic is simple, but the system access performance is limited
Solution Approach 1:
The system performs preliminary sorting of memory blocks and establishes the mapping relationship between non-sequential successive blocks and sequential disk logical addresses before actual access. This pre-preparation enables the memory controller to access multiple memories simultaneously during operation, significantly improving system access performance while keeping the control logic manageable through pre-computed mappings
Solution Approach 2:
The patent introduces an intermediary mapping mechanism that translates sequential disk logical addresses into non-sequential successive block addresses across multiple memories. This intermediary layer (the address mapping table) allows the host to issue simple sequential access commands while the memory controller translates them into simultaneous multi-memory operations, improving performance without increasing visible complexity
3Speed
If the memory controller uses sequential address mapping for multiple memories, then the mapping is simple, but the data transfer rate is not fully utilized
Solution Approach 1:
The memory controller performs preliminary sorting of blocks from multiple memories and pre-establishes the mapping between non-sequential successive blocks and sequential disk logical addresses. This pre-organization enables the system to fully utilize the data transfer rate by allowing simultaneous access to multiple memories, as the mapping complexity is resolved in advance rather than during data transfer
Solution Approach 2:
The address mapping is segmented into two independent parts: (1) the mapping relationship establishment, which is performed in advance by sorting blocks; and (2) the actual data transfer, which proceeds at full speed using the pre-established mappings. This segmentation allows the system to achieve high data transfer rates without the mapping complexity interfering with the actual data movement process
Data Source
AI summary
A method and a memory controller for accessing a plurality of memories are provided. The method includes sorting a plurality of blocks of a plurality of memories to correspond to a plurality of disk logical addresses that are sequentially sorted. The plurality of blocks of the plurality of memories include M first blocks of a first memory and N second blocks of a second memory, where M and N are each an integer greater than 1, and the M first blocks of the first memory and the N second blocks of the second memory in the plurality of disk logical addresses are sorted in a non-sequential successive order.