Memory Controller SRAM-DRAM Buffer Allocation for Speed and Chip Size

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Solution Overview

Problem

Existing memory systems face challenges in efficiently utilizing heterogeneous buffer memory components like SRAM and DRAM to bridge performance gaps between hosts and NAND flash memory, necessitating a method to optimize the allocation ratio between these memory types.

Innovation Solution

A memory controller that includes a processor and a buffer allocation circuit to control the allocation ratio between internal SRAM (main buffer memory) and external DRAM (sub-buffer memory), allowing for fixed or variable setting based on command types and performance monitoring.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If SRAM is used as buffer memory for high-speed performance, then data processing speed is improved, but chip size increases and cost increases

Engineering Contradiction:

Improvedata processing speedVSAvoidchip size

Core Design Contradiction:

SpeedVSVolume of moving object

Solution Approach 1:

The patent combines SRAM and DRAM buffer memories into a unified buffer management system. The memory controller includes both an SRAM buffer memory (first buffer memory) and a DRAM buffer memory (second buffer memory), and dynamically allocates buffer space between them based on operation modes and command types, thereby achieving high-speed performance while controlling chip size.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic buffer allocation where the allocation ratio between SRAM and DRAM buffer memories can be changed in real-time. The memory controller switches between different operation modes (first operation mode with first allocation ratio, second operation mode with second allocation ratio) based on command types and performance requirements, optimizing the balance between speed and chip size.

Inventive Principle:

Principle #15Dynamics

2Volume of moving object

If DRAM is introduced to reduce chip size, then chip size is reduced, but data processing speed decreases

Engineering Contradiction:

Improvechip sizeVSAvoiddata processing speed

Core Design Contradiction:

Volume of moving objectVSSpeed

Solution Approach 1:

The patent merges SRAM and DRAM buffer memories into a unified buffer management system. The memory controller includes both an SRAM buffer memory (first buffer memory) and a DRAM buffer memory (second buffer memory), and dynamically allocates buffer space between them based on operation modes and command types, thereby achieving high-speed performance while controlling chip size.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent applies different buffer allocation strategies for different command types. For commands requiring high-speed processing, a larger portion of buffer space is allocated to SRAM, while for other commands, DRAM buffer space is increased. This local optimization ensures that speed-critical operations use the faster SRAM while overall chip size remains controlled through DRAM usage.

Inventive Principle:

Principle #3Local quality

3Device complexity

If buffer allocation is fixed, then system complexity is reduced, but adaptability to different command types decreases

Engineering Contradiction:

Improvebuffer allocation control complexityVSAvoidadaptability to command types

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the buffer allocation parameters (allocation ratios) based on different operation modes and command types. The memory controller can switch between a first allocation ratio and a second allocation ratio, adjusting the buffer characteristics to match the requirements of different commands, thereby achieving adaptability without excessive complexity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250244914A1Memory controller for controlling allocation ratio of buffer memory, memory system including the same, and method of operating memory controller

Publication Date: 2025.07.31 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory system includes a memory controller configured to control a memory device and sub-buffer memory arranged outside the memory controller. The memory controller includes a processor configured to control a memory operation for the memory device, main buffer memory that is different from the sub-buffer memory and arranged in the memory controller, and a buffer allocation circuit configured to control an allocation ratio between the sub-buffer memory and the main buffer memory. The processor sets an operation mode of the buffer allocation circuit as an operation in which the allocation ratio is fixed.