Memory Controller Buffer Flush for Power Failure Data Integrity
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Solution Overview
Problem
Existing memory controllers face challenges in ensuring data reliability when main power is abnormally cut off or delivers incorrect voltage, as volatile buffer memories lose data and non-volatile memory devices require time to store data, leading to potential data loss.
Innovation Solution
A memory controller with a buffer memory and buffer memory controller that allocates buffer areas based on power information from the host and auxiliary power device, generating an area map table to temporarily store data and perform flush operations to secure data storage in non-volatile memory even during power abnormalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is stored in volatile buffer memory for fast access, then data access speed is improved, but data reliability deteriorates when main power is cut off
Solution Approach 1:
The system performs preliminary actions by allocating buffer areas in advance and maintaining area map tables that map logical addresses to physical addresses and buffer areas. This preparation ensures that when main power is cut off, the data can be immediately flushed to non-volatile memory without losing any information, thus resolving the contradiction between fast access and reliability during power abnormalities.
Solution Approach 2:
The auxiliary power device acts as an intermediary that bridges the volatile buffer memory and non-volatile memory during power abnormalities. It provides the necessary power to complete the data flushing process from the volatile buffer to non-volatile memory, ensuring data reliability is maintained while preserving the fast access capability of the buffer memory during normal operation.
2Quantity of substance
If buffer memory area is increased to store more data temporarily, then data storage capacity is improved, but power consumption increases during flush operation
Solution Approach 1:
The system dynamically adjusts buffer area allocation based on actual usage patterns and power availability. The buffer memory controller allocates buffer areas corresponding to memory areas and manages the area map table to optimize the mapping between logical and physical addresses. This dynamic management allows the system to increase storage capacity when needed while controlling power consumption during flush operations by flushing only the necessary data.
Solution Approach 2:
The system changes operational parameters by adjusting the allocation strategy of buffer areas based on power information from the host and auxiliary power device. When power is abundant, more buffer areas can be allocated to increase storage capacity. When power is constrained, the system adjusts the flush operation parameters to minimize power consumption while still ensuring data reliability.
3Reliability
If data is flushed to non-volatile memory immediately, then data reliability is improved, but data access speed deteriorates
Solution Approach 1:
The system segments the memory storage into multiple buffer areas corresponding to different memory areas, each with its own data to be stored. The buffer memory controller manages these segmented buffer areas and their mappings to physical memory addresses through the area map table. This segmentation allows the system to maintain fast access for individual buffer areas while ensuring reliability through selective flushing, rather than requiring immediate flush of all data.
Solution Approach 2:
The area map table is prepared in advance to store the mapping relationships between logical addresses, buffer areas, and physical addresses. This preliminary action enables fast data access during normal operation while ensuring that when flushing is needed, the system can efficiently locate and flush the correct data to non-volatile memory without sacrificing access speed for frequently accessed data.
Data Source
AI summary
The present technology includes a memory controller that allocates a new buffer memory area in a buffer memory or stores temporarily stored data in the buffer memory into a memory device based on a state of an auxiliary power device that supplies power to the memory device and the memory controller, and a power state of a host.