Memory Controller Buffer Usage Monitoring for Write Flush Optimization

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Solution Overview

Problem

Conventional memory systems waste memory space by performing periodic internal flush operations, even when user data is not ready to form a program unit, leading to unnecessary programming of dummy data.

Innovation Solution

A memory system with a controller that monitors buffer usage and generates flush control signals based on usage comparisons between current and previous periods, skipping unnecessary flush operations when user data is not ready to form a program unit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If periodic internal flush operations are performed, then data in the write buffer is transferred to the memory device, but memory space is wasted by programming dummy data when user data is not ready to form a program unit

Engineering Contradiction:
Improveflush operation efficiencyVSAvoidmemory space wastage
Core Design Contradiction:
ProductivityVSLoss of substance

Solution Approach 1:

The system dynamically adjusts the flush operation execution based on real-time buffer usage conditions. Instead of performing fixed periodic flush operations, the controller monitors whether the buffer usage amount meets a predetermined threshold and selectively executes flush operations only when conditions are satisfied, thereby avoiding wasteful dummy data programming while maintaining data transfer efficiency

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements a feedback mechanism where the controller continuously monitors the buffer usage amount and compares it against a threshold value. This feedback loop enables the system to make informed decisions about whether to execute a flush operation, ensuring that flush operations are performed only when sufficient user data is available, thus preventing memory space wastage

Inventive Principle:
Principle #23Feedback

2Speed

If flush operations are performed frequently, then data is transferred to memory device promptly, but unnecessary programming occurs when data is not ready to form a program unit

Engineering Contradiction:
Improvedata transfer speedVSAvoidunnecessary programming
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The system dynamically controls the timing and frequency of flush operations based on buffer usage conditions. By adjusting the flush operation execution according to whether the buffer usage amount meets the threshold, the system optimizes data transfer speed while eliminating unnecessary programming operations that would occur with frequent fixed-interval flushes

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The feedback mechanism monitors buffer usage and provides information to the controller to determine whether to execute a flush operation. This ensures that flush operations are triggered only when sufficient data is available, maintaining prompt data transfer when needed while preventing unnecessary programming when data is not ready

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11003590B2Memory system and operating method thereof
Publication Date: 2021.05.11 SK HYNIX INC
  • US11003590B2 patent drawing
  • US11003590B2 patent drawing
  • US11003590B2 patent drawing

AI summary

A memory system includes: a memory device storing host data provided from a host; and a memory controller managing and transferring the host data between the host and the memory device, wherein the memory controller comprises: a write buffer temporarily storing the host data to be transferred to the memory device; a buffer monitoring device checking a usage amount of the write buffer during a predetermined period; a buffer usage comparing device generating a flush control signal based on a usage amount comparison result by comparing the usage amount checked during a current period corresponding to the predetermined period with the usage amount checked during a previous period corresponding to the predetermined period; and a first flush device transferring the host data temporarily stored in the write buffer to the memory device in response to the flush control signal.