Memory Controller Buffer Reordering for Disordered Flash Data

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Solution Overview

Problem

Existing Flash memory devices face challenges in improving access speed, particularly due to disordered data transfer and inefficient handling of access information.

Innovation Solution

A memory controller architecture that includes a buffer memory, memory interface, microprocessor, and host interface, which reads and writes data portions with assigned tag values, generates descriptors in chronological order, and uses a routing manager and DMA engine to ensure correct data transfer order.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is read from memory device in parallel portions, then data transfer speed is improved, but data order becomes disordered

Engineering Contradiction:

Improvedata transfer speedVSAvoiddata order

Core Design Contradiction:

SpeedVSStability of the object's composition

Solution Approach 1:

The patent divides data into multiple portions with different tag values (first portion, second portion, third portion, etc.) that can be read in parallel from the memory device. Each portion is assigned a unique tag to enable later identification and reordering, thus achieving both parallel reading speed and data order stability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a buffer memory as an intermediary component between the memory device and the host device. The buffer memory temporarily stores the disordered data portions and enables their reordering before transmission to the host, acting as a mediator that decouples the parallel reading process from the sequential data delivery requirement.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If descriptors are generated after all data transfer is complete, then data integrity is ensured, but processing time increases

Engineering Contradiction:

Improvedata integrityVSAvoidprocessing time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent generates descriptors during the data transfer process itself, rather than waiting for completion. When a data portion is transferred to the buffer memory, its corresponding descriptor is generated immediately with the correct sequential order information. This preliminary generation of descriptors maintains data integrity while eliminating idle processing time.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent ensures continuous processing by generating descriptors concurrently with data transfer operations. The descriptor generation process does not wait for data transfer to complete but proceeds continuously as each portion arrives at the buffer, maximizing utilization of processing resources and eliminating idle time.

Inventive Principle:

Principle #20Continuity of useful action

3Stability of the object's composition

If microprocessor waits for chronological order of access information, then data order is maintained, but productivity decreases

Engineering Contradiction:

Improvedata orderVSAvoidmicroprocessor efficiency

Core Design Contradiction:

Stability of the object's compositionVSProductivity

Solution Approach 1:

The patent implements a self-service mechanism where the buffer memory automatically manages the reordering of data portions based on tag values without requiring microprocessor intervention. The buffer memory includes a reordering unit that autonomously sorts incoming data portions into chronological order, freeing the microprocessor to perform other productive tasks while maintaining data order integrity.

Inventive Principle:

Principle #25Self-service

4Speed

If data portions are read in parallel, then access speed is improved, but device complexity increases

Engineering Contradiction:

Improveaccess speedVSAvoidmemory controller structure

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent designs the buffer memory with multi-functional capabilities: it serves as both a temporary storage location for parallel data portions and an automatic reordering unit. The buffer memory's reordering unit uses tag values to automatically sort data portions chronologically, eliminating the need for separate complex control logic and reducing overall device complexity while maintaining parallel access speed.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12223173B2Memory controller and data processing method for processing disordered read-out data

Publication Date: 2025.02.11 SILICON MOTION INC

AI summary

A data processing method includes reading a memory device in response to a read command to respectively read multiple portions of predetermined data; respectively writing the portions in a buffer memory to complete data transfers of the portions of the predetermined data; sequentially providing access information corresponding to each portion of the predetermined data in response to completion of the data transfer of the corresponding portion; obtaining the access information of the predetermined data and accordingly generating multiple descriptors in chronological order of obtaining the access information; receiving and buffering the descriptors in a descriptor pool; sequentially selecting a latest descriptor from the descriptor pool according to a tag value and providing the latest descriptor to a direct memory access engine; and reading the buffer memory according to the latest descriptor to obtain at least a portion of the predetermined data by the direct memory access engine.