Memory Controller Buffering for Non-Volatile Memory Wear Reduction

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Solution Overview

Problem

In computing systems, frequent writing requests to non-volatile memory due to size differences between data processed in volatile memory and stored in non-volatile memory lead to processor burden and potential shortening of non-volatile memory lifetime.

Innovation Solution

A method involving a memory controller with a buffer that sequentially receives and stores data segments until reaching a cumulative size, allowing efficient programming in non-volatile memory by transmitting data in processing units, reducing the number of instructions and programming events.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is written to non-volatile memory in small segments matching host processing units, then data transmission efficiency is improved, but the number of writing requests increases and processor burden increases

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidnumber of writing requests
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing incoming host data into smaller units that match the non-volatile memory's write constraints, while simultaneously grouping these segmented data units into larger write commands. This dual segmentation strategy allows the system to maintain compatibility with both host processing units and memory write constraints, reducing the number of writing requests while preserving data transmission efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a buffer memory as an intermediate dimension between the host and non-volatile memory. This buffer serves as a temporary storage space where data can be accumulated and reorganized, allowing the system to decouple the data reception rate from the data write rate. By adding this temporal and spatial dimension, the system can process data in small segments from the host while writing in larger, more efficient batches to the memory.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If multiple writing requests are issued to non-volatile memory, then data can be stored in small units matching host processing, but non-volatile memory lifetime is shortened due to wear-out

Engineering Contradiction:
Improvedata size compatibilityVSAvoidnon-volatile memory lifetime
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent merges multiple small data segments accumulated in the buffer into a single larger write command before transmitting to the non-volatile memory. This merging operation reduces the total number of write requests issued to the memory, thereby decreasing wear and extending memory lifetime while still maintaining the ability to handle various data sizes from the host through the buffering mechanism.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The buffer memory acts as an intermediary between the host and non-volatile memory, absorbing the mismatch in data size requirements. It receives data in small units compatible with host processing, then accumulates and forwards data in larger units optimized for memory writes. This intermediary layer protects the non-volatile memory from excessive write operations while maintaining adaptability to different data sizes.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If data is accumulated in buffer until cumulative size reaches second size, then number of programming operations is reduced, but data transmission delay increases

Engineering Contradiction:
Improveprogramming operation efficiencyVSAvoiddata transmission delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements dynamic buffer management where the buffer size threshold for triggering a write operation can be adjusted based on system conditions. When the host can keep up with write operations, the buffer threshold can be set higher to maximize write efficiency. When the host generates data faster or the system requires lower latency, the threshold can be reduced. This dynamic adaptation allows the system to balance programming operation efficiency against data transmission delay in real-time.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10445014B2Methods of operating a computing system including a host processing data of first size and a storage device processing data of second size and including a memory controller and a non-volatile memory
Publication Date: 2019.10.15 SAMSUNG ELECTRONICS CO LTD
  • US10445014B2 patent drawing
  • US10445014B2 patent drawing
  • US10445014B2 patent drawing

AI summary

A method of operating a memory controller is provided. The method of operating a memory controller according to an exemplary embodiment of the present inventive concepts includes sequentially receiving, by the memory controller, first data segments each having a first size from a host, sequentially storing, by the memory controller, the first data segments in the buffer until a sum of sizes of changed data among data stored in a buffer included in the memory controller is a second size, and programming, by the memory controller, the changed data having the second size in a memory space of a non-volatile memory as a second data segment.