Memory Controller Burst Access for DSP Efficiency
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Solution Overview
Problem
Digital signal processors face limitations in memory access schemes, leading to inefficiencies in processing algorithms like FFT, beamforming, and neural networks due to restrictions on bandwidth, latency, and processing time, as existing bus standards only support consecutive word access and lack signals to specify memory bank access schemes.
Innovation Solution
A method for accessing memory in digital signal processors that involves generating burst transactions with programmable stride and specifying memory bank access schemes using user-available signals, such as AWUSER and ARUSER in the AXI standard, to group multiple memory accesses into a single transaction and optimize memory access patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory access schemes are used with standard bus protocols, then compatibility with existing systems is maintained, but processing efficiency and bandwidth utilization deteriorate due to restrictions on non-consecutive access patterns
Solution Approach 1:
The patent implements dynamic memory access schemes where the memory controller can adaptively select between different access patterns (consecutive, strided, bank-interleaved) based on the specific algorithm requirements. This allows the system to optimize for processing efficiency when needed while falling back to standard patterns for compatibility, resolving the contradiction between productivity and complexity.
Solution Approach 2:
The invention changes key parameters of memory access by introducing programmable stride values and bank selection signals that modify the standard sequential access pattern. By allowing these parameters to be dynamically adjusted based on algorithm requirements (e.g., FFT, beamforming), the system achieves higher processing efficiency without requiring a completely new access scheme.
2Productivity
If burst transactions are extended to support non-consecutive memory locations, then data transfer efficiency improves, but compatibility with existing bus standards deteriorates
Solution Approach 1:
The patent introduces a memory controller as an intermediary between the standard bus interface and the memory array. This intermediary translates standard bus transactions into optimized memory access patterns, including non-consecutive burst transactions. The intermediary maintains compatibility with existing bus standards while enabling advanced access patterns, thus resolving the contradiction between productivity and adaptability.
Solution Approach 2:
The invention segments the memory access function into distinct components: the standard bus interface layer, the memory controller translation layer, and the physical memory access layer. This segmentation allows each layer to operate independently, with the controller layer handling the complexity of non-consecutive burst transactions while presenting a standard interface to the bus, thereby maintaining compatibility while improving data transfer efficiency.
3Loss of time
If multiple memory accesses are grouped into single burst transactions, then computational latency reduces, but the requirement for complex address mapping and bank selection increases
Solution Approach 1:
The patent implements preliminary action by pre-configuring memory bank assignments and access patterns based on the specific algorithm being executed. Before the actual data processing begins, the memory controller is programmed with the appropriate stride values, bank selections, and burst parameters. This preliminary setup enables efficient burst transactions during execution without requiring complex real-time address mapping, thus reducing computational latency while managing complexity through advance preparation.
Data Source
AI summary
An embodiment method of accessing a memory for reading and/or writing data comprises generating a memory transaction request comprising a burst of memory access requests towards a set of memory locations in the memory, the memory locations having respective memory addresses. The method further comprises transmitting via an interconnect bus to a memory controller circuit coupled to the memory a first signal conveying the memory transaction request and a second signal conveying information for mapping the burst of memory access requests onto respective memory addresses of the memory locations in the memory. The method further comprises computing, as a function of the information conveyed by the second signal, respective memory addresses of the memory locations, and accessing the memory locations to read data from the memory locations and/or to write data into the memory locations.