Memory Controller Command Generation for Burst Write
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Solution Overview
Problem
Existing CPU methods for functions like memset consume significant time and memory due to repeated code execution and limited burst write capabilities, especially when writing the same data to memory.
Innovation Solution
An electronic device with a processing circuit, bus, and memory controller is designed to generate and process write commands efficiently, allowing for continuous memory writing operations by extending command processing to the bus or memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CPU repeatedly executes multiple codes to write the same data to memory, then the data transfer is completed, but the processing time and memory usage increase significantly
Solution Approach 1:
The patent introduces a memory management unit (MMU) as an intermediary between the CPU and memory. The MMU receives a single write command from the CPU containing a starting address and target value, then automatically generates multiple consecutive write commands to the memory, eliminating the need for the CPU to repeatedly execute write operations.
Solution Approach 2:
The memory management unit performs self-service by autonomously generating the sequence of write commands needed to complete the data transfer. Once the CPU issues the initial write command, the MMU independently handles the repeated writing operations without further CPU intervention, allowing the CPU to proceed with other tasks.
2Reliability
If the CPU repeatedly executes multiple codes to write the same data to memory, then the data transfer is completed, but the program space and memory usage increase
Solution Approach 1:
The memory management unit acts as an intermediary that eliminates the need for the CPU to store and execute multiple repeated write commands. The MMU contains the logic to generate the command sequence, reducing the program space requirements in the CPU.
Solution Approach 2:
The patent extracts the repeated command generation logic from the CPU and places it in the memory management unit. This separation removes the burden of storing multiple write commands from the CPU's program space, as only a single initial write command needs to be stored and executed by the CPU.
3Adaptability or versatility
If burst write is not implemented or the burst write length of the CPU is limited, then the system can operate with standard write operations, but the data transfer efficiency decreases
Solution Approach 1:
The memory management unit serves as an intermediary that implements burst write functionality even when the CPU lacks native burst write capability. The MMU receives a single write command from the CPU and automatically generates a burst sequence of write commands to the memory, achieving high-efficiency data transfer without requiring CPU modifications.
Solution Approach 2:
The system dynamically adapts to different CPU capabilities. When the CPU has limited or no burst write capability, the MMU dynamically generates the appropriate command sequence to achieve efficient memory writing. This dynamic command generation allows the system to maintain high productivity across different CPU architectures.
Data Source
AI summary
An electronic device capable of accessing a memory and a data writing method are provided. The electronic device includes a processing unit, a bus, and a memory controller. The processing unit includes a bus interface control circuit, and the processing unit generates a first write command through the bus interface control circuit according to a memory access command. The memory access command contains a first memory address and a target value, and the first write command contains the first memory address and the target value. The bus is coupled to the bus interface control circuit and configured to generate a second write command according to the first write command. The second write command contains a second memory address and the target value. The memory controller is coupled to the bus and configured to write the target value into the memory according to the second memory address.