Memory Controller Bus Arbitration for Simultaneous Data Transfer and Search
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Solution Overview
Problem
Current memory systems face inefficiencies in memory access due to sequential processing of data transfer and search operations, leading to increased processing time when cache misses occur, as they require separate stages for data transfer and search.
Innovation Solution
The implementation of a memory system with a direct memory access controller and a second search circuit that performs a transfer-in-progress search during data transfer, allowing simultaneous data transfer and search operations, thereby reducing processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If sequential processing of data transfer and search operations is used, then device complexity is reduced, but processing time increases
Solution Approach 1:
The patent combines the data transfer operation (performed by the direct memory access controller) and the search operation (performed by the second search circuit) into a single simultaneous process. The second search circuit searches for cache target data during its transfer from nonvolatile memory to cache memory, eliminating the need for sequential execution and reducing processing time.
Solution Approach 2:
The patent enables continuous useful action by allowing the search operation to proceed continuously during the data transfer operation. The second search circuit continuously searches for the cache target data as it is being transferred, ensuring that no time is lost between transfer completion and search initiation.
2Productivity
If separate stages for data transfer and search are used, then ease of operation is improved, but productivity decreases
Solution Approach 1:
The patent merges the data transfer stage and search stage into a single integrated operation. The direct memory access controller transfers cache target data while the second search circuit simultaneously searches for this data, improving memory access speed without requiring complex multi-stage coordination from the operator perspective.
Data Source
AI summary
A memory system includes a nonvolatile memory and a memory controller including a bus, a cache memory, a direct memory access controller, a first search circuit, a second search circuit, and a transfer control circuit. The direct memory access controller transfers cache target data stored in the nonvolatile memory to the cache memory. The second search circuit searches the cache target data that is being transferred. The transfer control circuit assigns, in response to the second search circuit detecting a search hit, to the transfer control circuit and the second search circuit, a bus right which has been assigned at least to the cache memory for the transfer of the cache target data to the cache memory, and obtains, by using the assigned bus right, a search result from the second search circuit via the bus.