Memory Controller Multiplexed Bus Identification Signal
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Solution Overview
Problem
The existing technique for reducing signal lines in semiconductor devices is not applicable to multiplex interfaces, where address/command and data signals are transmitted through the same line, limiting the ability to independently connect data buses and selection signal lines to multiple memories.
Innovation Solution
A memory controller that allocates command, address, and data signals to be transmitted through the same bus line, with an identification signal shared among memory devices to identify and manage these signals, allowing for reduced signal lines and maintaining performance by suspending data transfer in one device to issue commands and addresses to another.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a multiplex interface is used to transmit address/command and data signals through the same signal line, then the number of signal lines is reduced, but the ability to independently connect data buses and selection signal lines to multiple memories is lost
Solution Approach 1:
The patent segments the signal transmission by introducing identification signals that distinguish between different memory devices and signal types (address/command vs. data). This allows the single multiplexed signal line to be logically divided into separate channels for different purposes, enabling independent control similar to having separate physical lines while using a shared physical medium.
Solution Approach 2:
The identification signal acts as an intermediary that mediates between the multiplexed signal line and the multiple memory devices. It provides the necessary information to distinguish which memory device should receive which type of signal, enabling the system to function as if separate dedicated lines were present for each memory device.
2Ease of operation
If data transfer is suspended to issue commands to another memory device, then command control is improved, but data transfer performance may deteriorate
Solution Approach 1:
The patent implements periodic action by alternating between data transfer operations and command issuance operations in a structured sequence. The identification signal enables the system to periodically switch between transmitting data and transmitting commands, ensuring that command control requirements are met while maintaining a rhythmic, predictable pattern that minimizes disruption to overall data transfer performance.
Data Source
AI summary
In a memory controller, command, address and data are allocated to transmit the command, the address and the data to each of the plurality of memory devices through the same bus signal line and an identification signal to identify the command, the address and the data on the bus signal line is allocated to a memory common signal line in common among the plurality of memory devices to transmit the identification signal. When the memory controller indicates the data through the identification signal so as to make a first memory device transfer the data through the bus signal line, the memory controller makes the data transfer by the first memory device suspended, indicates the command through the identification signal so as to issue the command to a second memory device, and indicates the address through the identification signal so as to issue the address to the second memory device.