Memory Controller Bus Topology for High-Speed Storage
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Solution Overview
Problem
Existing memory systems face challenges in increasing operating speed without compromising storage capacity, particularly when the number of memory modules connected to a single channel is increased, leading to loading issues that hinder frequency enhancements.
Innovation Solution
A memory system architecture that includes a memory controller directly connected to a first memory module via a point-to-point bus, with subsequent memory modules connected to the first module through a multi-drop bus, utilizing a buffer device with re-driving capabilities to manage data transmission and timing adjustments, allowing for increased operating speed without reducing storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory modules connected to one channel is increased, then storage capacity is improved, but loading from the memory controller increases making it difficult to increase operating frequency
Solution Approach 1:
The patent segments the memory modules into two distinct groups with different connection topologies: a first memory module directly connected to the memory controller via a first memory bus, and second through k-th memory modules connected via a multi-drop second memory bus. This segmentation allows the directly connected first memory module to operate at higher frequencies with reduced loading on the controller, while maintaining overall storage capacity through the inclusion of multiple second through k-th memory modules.
2Quantity of substance
If the number of memory modules connected to one channel is increased, then storage capacity is improved, but loading from the memory controller increases
Solution Approach 1:
The patent introduces an intermediary connection structure where the first memory module serves as a mediator between the memory controller and the second through k-th memory modules. The first memory module is directly coupled to the controller via a point-to-point connection, while subsequent modules connect through a multi-drop bus to the first module. This intermediary arrangement reduces the direct loading on the memory controller by distributing the memory access paths.
Data Source
AI summary
A memory system includes a memory controller, a first memory module and second through k-th memory modules. The first memory module is directly coupled to the memory controller without any other memory modules communicatively coupled therebetween, through a first memory bus, and the first memory module exchanges first data with the memory controller. The second through k-th memory modules are coupled to the first memory module with a multi-drop connection through a second memory bus and the second through k-th memory modules exchange second data with the memory controller via the first memory module.