Memory Controller Non-Blocking Cache Management for Multi-Queue Systems
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Solution Overview
Problem
Existing data storage devices face performance delays due to the blocking method used in data caching, which causes all requests to be delayed when processing one request, leading to lower performance in multi-queue systems.
Innovation Solution
A non-blocking data caching method is implemented in a memory controller that allocates new entries for write commands and transfers data in specific states, such as PEND, PEND OLD, or CACHE, allowing simultaneous processing of read and write operations without unnecessary buffer copies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a blocking method is used to maintain data consistency, then data consistency is improved, but processing speed and performance deteriorate because all requests are delayed when one request is being processed
Solution Approach 1:
The patent segments the cache management into multiple independent queues (read queue and write queue) with separate entry structures. Each queue can be processed independently, allowing read requests to be handled without blocking write operations and vice versa. The cache is divided into multiple entries (first entry, second entry, etc.) that can be managed separately, enabling concurrent processing of multiple requests while maintaining data consistency through structured state transitions.
Solution Approach 2:
The patent implements dynamic state transitions for cache entries based on operation type and completion status. Entries transition between states (e.g., READ/PEND/DEL for reads, WRITE/PEND/DEL for writes) allowing the system to adapt its behavior based on current operations. This dynamic management enables the cache to handle overlapping read and write operations efficiently, improving throughput while maintaining consistency through state-aware processing.
2Reliability
If a sync method is used to process requests sequentially, then data consistency is maintained, but response time increases and performance of multi-queue systems deteriorates
Solution Approach 1:
The patent divides the cache into multiple independent entries (first entry, second entry, third entry, etc.) that can be processed concurrently. Each entry maintains its own state machine, allowing the system to process multiple requests in parallel without interfering with data consistency. This segmentation enables multi-queue systems to achieve true concurrent processing while maintaining consistency through structured entry management.
Solution Approach 2:
The patent enables continuous processing of requests by implementing non-blocking operations where completed operations immediately free up cache entries for new operations. Read operations can proceed continuously without waiting for write completions, and write operations can queue up without blocking the read path. This continuity eliminates idle time and maximizes throughput while maintaining data consistency through state-aware processing.
3Reliability
If traditional cache management is used, then data consistency is maintained, but buffer usage increases due to unnecessary internal buffer copies
Solution Approach 1:
The patent extracts the unnecessary buffer copy operation from the cache management process. By implementing direct entry-to-host data transfer for read operations and direct host-to-entry data transfer for write operations, the patent eliminates the need for intermediate buffer copies. This extraction reduces buffer usage while maintaining data consistency through structured state transitions and entry management.
Solution Approach 2:
The patent enables cache entries to serve themselves by implementing direct data paths between entries and host memory. Read entries can be directly accessed by the host without requiring intermediate buffer copies, and write entries can directly receive data from the host. This self-service approach eliminates unnecessary data movement and reduces buffer usage while maintaining consistency through state-aware access patterns.
Data Source
AI summary
A method of operating a memory controller includes allocating a new entry whenever a write command is input from a host; and transferring data corresponding to an entry in a specific state among a plurality of states to the host in response to a read command output from the host, wherein the plurality of states are a FREE state, a WRITE state, a WRITE OLD state, a READ state, a PEND state, a PEND OLD state, a CACHE state, and a DEL state, and the specific state is at least one of the PEND state, the PEND OLD state, or the CACHE state.