Memory Controller Cache for Mapping Access Latency
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Solution Overview
Problem
Current memory systems face inefficiencies in reading data from buffer memory devices due to the use of DRAM, which degrades read performance by requiring direct access to the buffer memory device for logical-physical address mapping information.
Innovation Solution
Implementing a cache memory to store and cache logical-physical address mapping information, allowing the memory system to refer directly to this information from the cache instead of the buffer memory device, thereby improving read performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM buffer memory device is used to store logical-physical address mapping information, then data can be stored, but read performance degrades due to requiring direct access to the buffer memory device
Solution Approach 1:
The patent implements a cache memory that pre-loads and stores frequently accessed logical-physical address mapping information before it is needed for read operations. By performing the address mapping lookup in advance and caching the results, the system eliminates the need for real-time access to the DRAM buffer memory device during data read operations, thus improving read performance and reducing access time.
Solution Approach 2:
The patent introduces a cache memory as an intermediary component between the host control circuit and the DRAM buffer memory device. This cache memory acts as a mediator that holds frequently accessed mapping information, allowing the host control circuit to retrieve address mappings quickly without directly accessing the slower DRAM buffer memory device, thereby resolving the performance bottleneck.
2Loss of time
If direct access to buffer memory device is used for address mapping information, then data retrieval is possible, but latency increases
Solution Approach 1:
The cache memory performs preliminary loading of logical-physical address mapping information into its faster memory structure. This pre-positioning of data allows subsequent read operations to access mapping information immediately without the latency associated with direct DRAM buffer memory device access, thereby reducing data retrieval time and increasing retrieval speed.
Solution Approach 2:
The patent creates a copy of the frequently accessed logical-physical address mapping information and stores it in the cache memory. This copy serves as a rapid-access replica that eliminates the need for repeated accesses to the original DRAM buffer memory device, significantly reducing latency and improving data retrieval speed.
Data Source
AI summary
A memory system includes a nonvolatile memory device, a buffer memory device storing logical-physical address mapping information, and a memory controller controlling operations of the nonvolatile and buffer memory devices. The memory controller comprises a cache memory, a host control circuit, a flash translation section, and a flash control circuit. The host control circuit receives a read command and a read logical address from a host, reads mapping information corresponding to the read logical address from the buffer memory device, and caches the mapping information in the cache memory, the mapping information corresponding to the logical-physical address mapping information stored in the buffer memory device. The flash translation section reads a read physical address mapped to the read logical address from the mapping information. The flash control circuit reads data corresponding to the read command from the nonvolatile memory device based on the read physical address.