Memory Controller Cache Read Stability via Sensing Section Code

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Solution Overview

Problem

Existing storage devices face challenges in ensuring accurate data sensing operations due to overlapping power requirements between data output and sensing sections, leading to potential power noise and instability during cache read operations.

Innovation Solution

A memory controller is designed to transmit cache read commands and status read commands to the memory device, utilizing a sensing section code to determine if the device is in a sensing operation, thereby preventing simultaneous data output and sensing, ensuring accurate and stable data retrieval.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data output operation is performed simultaneously with sensing operation, then productivity is improved, but measurement precision deteriorates due to power noise

Engineering Contradiction:
Improvecache read operation speedVSAvoiddata sensing accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent segments the cache read operation into distinct phases by introducing a sensing section code that identifies when the memory device is in a sensing operation. This segmentation allows the controller to separate data output operations from sensing operations, preventing their overlap while maintaining efficient operation flow.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by having the memory device proactively provide a sensing section code to indicate its current operational state before any potential conflict occurs. This allows the controller to anticipate and prevent overlapping operations by adjusting the data-out command timing based on the sensed state information.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If data output command is transmitted without sensing state check, then device complexity is reduced, but reliability deteriorates due to unstable sensing operations

Engineering Contradiction:
Improvecontroller operation simplicityVSAvoidsensing operation stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements feedback by having the memory device continuously provide sensing section code information to the controller. This feedback mechanism enables the controller to make informed decisions about when to issue data-out commands, ensuring that data output operations only occur when sensing operations are not in progress, thereby maintaining reliable sensing operations.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If sensing section code is monitored to prevent operation overlap, then measurement precision is improved, but loss of time increases due to additional status checks

Engineering Contradiction:
Improvedata sensing accuracyVSAvoidstatus read command overhead
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent merges the status monitoring function into the existing cache read operation flow by using the sensing section code that is already generated during normal memory operations. This integration allows the controller to obtain sensing state information as a byproduct of normal operation without requiring separate monitoring mechanisms, minimizing additional time overhead.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10552328B2Storage device and operating method thereof
Publication Date: 2020.02.04 MIMIRIP LLC
  • US10552328B2 patent drawing
  • US10552328B2 patent drawing
  • US10552328B2 patent drawing

AI summary

There are provided a memory controller for controlling a memory device to perform a more stable sensing operation, a storage device including the memory controller, and an operating method of the storage device. A memory controller includes: a processor for transmitting a cache read command to a memory device and then transmitting a status read command to the memory device; and a cache read controller for outputting a data-out command to the memory device according to a sensing section code included in a status read response transmitted by the memory device in response to the status read command.