Memory Controller Function Calls for Lower-Latency Data Access

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Solution Overview

Problem

Existing memory systems experience performance degradation due to increased delay times and overhead in data processing caused by various access methods, leading to inefficient data processing.

Innovation Solution

A memory system with a controller that includes multiple processing units, which allocates memories based on performance modes and scheduling policies to optimize data processing by reducing the number of accesses, using a call command to provide result data efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple access methods are used to process data requests from external devices, then the memory system can handle various data processing tasks, but the delay time and overhead increase leading to performance degradation

Engineering Contradiction:
Improvedata processing capabilityVSAvoidaccess delay time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The memory system is segmented into multiple processing units (first processing unit, second processing unit, etc.), each capable of independently handling different data processing tasks. This segmentation allows parallel processing of multiple requests simultaneously, reducing the overall access delay time while maintaining versatility in handling various data processing tasks

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The controller pre-allocates specific memories to different processing units based on their capabilities and the nature of tasks they handle. This preliminary allocation ensures that when data processing requests arrive, the appropriate processing unit can immediately begin processing without additional allocation delays, thus reducing access delay time while maintaining adaptability

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple processing units are allocated to handle different data processing tasks, then the operational performance improves, but the device complexity increases

Engineering Contradiction:
Improveoperational performanceVSAvoidcontroller structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Multiple processing units are designed with identical or similar functional capabilities, allowing each unit to handle various types of data processing tasks. This universality means that while there are multiple processing units increasing complexity, each unit is a standardized component that can perform multiple functions, making the increased complexity manageable and beneficial for parallel processing to improve operational performance

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The controller dynamically allocates and manages processing units based on the nature of incoming data processing requests. This dynamic management allows the system to optimize resource utilization by assigning appropriate processing units to specific tasks, improving operational performance while the standardized dynamic allocation protocol keeps the control logic manageable despite having multiple processing units

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250315296A1Controller, memory system and computing system
Publication Date: 2025.10.09 SK HYNIX INC
  • US20250315296A1 patent drawing
  • US20250315296A1 patent drawing
  • US20250315296A1 patent drawing

AI summary

When an application of a host device accesses data of a memory system through an indirect memory access method, a call command which is set for processing of a corresponding task is transmitted to the memory system, and the memory system calls a previously stored function on the basis of the call command and provides result data obtained according to the indirect memory access method to the application. Therefore, data processing performance using the memory system may be improved while reducing the number of accesses between the host device and the memory system and a time.