Memory Controller Rewriting for Faster Multi-Level Cell Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing use of multi-level memory cell transistors in semiconductor devices leads to deteriorated read limit performance, limiting data transfer speed despite advancements in host interface speed, and traditional methods to enhance read performance, such as increasing page size or number of dies, are either costly or inefficient.
Innovation Solution
A memory system and control method that changes the writing method for recorded data to use a method with a smaller number of cell bits before reading, enhancing read performance by rewriting the recorded data using a method with a smaller number of bits, thereby reducing the effective read time, thereby enhancing the limit read performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level memory cell transistors are used to increase storage capacity, then storage density is improved, but read limit performance deteriorates
Solution Approach 1:
The patent applies preliminary action by performing a preparation write operation before the actual read operation. The memory controller rewrites the data in the memory cells using a writing method with fewer cell bits (e.g., SLC or MLC) prior to reading, so that when data is read subsequently, it can be read at high speed using the simplified writing method, thereby resolving the contradiction between high storage density and fast read performance
Solution Approach 2:
The patent applies dynamics by dynamically switching between different writing methods based on the operational context. The memory controller determines whether to use a multi-level writing method for normal storage or a single-level writing method for high-speed read preparation, allowing the system to adapt its behavior based on whether storage capacity or read speed is the priority
2Reliability
If traditional methods to enhance read performance (increasing page size or number of dies) are used, then read performance is improved, but cost increases
Solution Approach 1:
The patent applies parameter changes by changing the writing method parameter (number of cell bits) dynamically. Instead of physically changing the memory architecture (increasing page size or number of dies), the system changes the operational parameters by selecting different writing methods (SLC, MLC, TLC, QLC) based on the need for high-speed reading versus high-storage density, thereby achieving performance improvement without increased manufacturing complexity or cost
Data Source
AI summary
According to one embodiment, a memory system includes an array of memory cells that store two or more bits of data each, and a memory controller to control writing data into the memory cells and reading from the memory cells. When a first command is received from a host, the memory controller reads data designated by the first command from the array and then rewrites the read data back into the array using a writing method in which a lower number of bits per memory cell is written than the originally stored manner of the read data. When a read command designating the rewritten data is received from the host, the memory controller reads from the array and transfers it to the host.