Memory Controller Channel Utilization Distribution

The patent segments memory transactions into different priority levels, separating real-time transactions (camera, display) from non-real-time transactions (processing cores, graphics). The memory controller includes separate arbitration logic for each priority level, allowing real-time transactions to be handled with guaranteed timing while non-real-time transactions use standard FIFO scheduling. This segmentation resolves the contradiction by providing reliable timing for critical circuits without requiring complete redesign of the entire memory control system.

The patent introduces a transaction priority identifier as an intermediary element that carries timing requirements through the memory system. This identifier is inserted by the master circuit and used by the memory controller to determine arbitration priority. The intermediary mechanism allows the system to automatically route transactions appropriately without complex direct control logic between all circuits, resolving the contradiction between reliability and complexity.

The patent segments the data bus into multiple independent channels, each capable of handling transactions separately. The memory controller includes channel selection logic that automatically distributes transactions across available channels based on current utilization. This segmentation increases total bandwidth while keeping individual channel management simple, resolving the contradiction between productivity and complexity.

The patent implements dynamic channel selection where the memory controller continuously monitors channel utilization and adapts its distribution strategy in real-time. When certain channels become congested, the controller automatically routes transactions to less-utilized channels. This dynamic adaptation allows the system to maintain high productivity across multiple channels without requiring complex static distribution logic.