Memory Controller Charge-Leakage Recovery for NAND Retention Errors
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Solution Overview
Problem
NAND flash memory devices face issues with data retention and read disturb, leading to increased write amplification factor and shortened service life due to the need for frequent data relocation and inefficient error correction.
Innovation Solution
A memory controller that enters a high-order error correction mode when error bit count exceeds a threshold, identifies charge leakage as the cause, and applies programming pulse signals in an incrementally stepped pulse manner to remedy the issue, reducing the need for data relocation and extending the device's lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent data relocation is performed to address data retention and read disturb issues, then data reliability is improved, but write amplification factor increases and service life shortens
Solution Approach 1:
The memory block performs self-recovery by complementarily programming cells with charge leakage issues, eliminating the need for frequent data relocation to other blocks. The system detects charge leakage through error bit counting and automatically remediates by applying additional programming pulses to the affected block, allowing the memory to service itself rather than requiring data migration operations
Solution Approach 2:
The system performs preliminary detection of charge leakage conditions through error bit counting during normal operation, and proactively applies complementary programming pulses before data retention or read disturb issues escalate. This preliminary intervention prevents the need for subsequent data relocation operations that would increase write amplification
2Device complexity
If traditional error correction modes are used, then processing simplicity is maintained, but data reliability deteriorates when error bit count exceeds threshold
Solution Approach 1:
The error correction system dynamically adapts its operation mode based on the detected error bit count. When error bits exceed a threshold, the system transitions from standard error correction to high-order error correction mode, which enters high-order states for detailed analysis and applies complementary programming selectively. This dynamic adaptation maintains simplicity for low-error scenarios while providing enhanced reliability when needed
Solution Approach 2:
The system changes operational parameters based on error conditions: when error bit count exceeds the threshold, it modifies the correction strategy by entering high-order states and applying complementary programming pulses with specific pulse counts. This parameter change allows the system to handle high-error scenarios effectively without overcomplicating low-error operations
3Measurement precision
If read reference voltages are reduced for high-order states, then charge leakage detection precision is improved, but manufacturing precision requirements increase
Solution Approach 1:
The system applies different read reference voltage strategies to different states: standard reference voltages for low-order states and reduced reference voltages specifically for high-order states where charge leakage is more prevalent. This localized approach improves detection precision for problematic high-order states without unnecessarily complicating the reading of other states
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces write amplification factor and extends the service life of the memory device by addressing charge leakage and read disturb, improving data reliability and system performance.
Implementation Method 1
checking whether an inducement type of the error bit count is charge leakage
Implementation Method 2
remedying step of complementarily applying programming pulse signals to the memory block
Data Source
AI summary
Implementations of the present disclosure disclose a memory controller and an operation method thereof, and a memory system. The operation method of the memory controller can include a starting step of entering a high-order error correction mode when the data read from a memory block belongs to correctable error correction code data and an error bit count of the memory block is greater than a specific value, a detection step of checking whether an inducement type of the error bit count is charge leakage, and a remedying step of complementarily applying programming pulse signals to the memory block if the inducement type is the charge leakage. The present application reduces the refresh probability of the memory block, reduces the write amplification factor, and thus extends the service life of the memory device.