Memory Controller Chase Decoding for Multi-Error Flash Reads
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Solution Overview
Problem
In storage devices using flash memory, read errors can occur due to noise and elapsed time, and existing error correcting codes like BCH and RS codes struggle with high-speed decoding when the number of error symbols exceeds a certain threshold, leading to incorrect or failed decoding.
Innovation Solution
A memory controller that employs bounded distance decoding and chase decoding techniques, generating test patterns to correct errors by rewriting symbols and performing soft-decision decoding, which adapts the range of error symbol positions based on soft-decision information to improve decoding capability while reducing calculation overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing error correcting codes (BCH and RS codes) are used for decoding, then decoding can be performed, but decoding fails or becomes incorrect when the number of error symbols exceeds a certain threshold
Solution Approach 1:
The patent applies dynamics by making the decoding process adaptive through iterative testing. The decoder dynamically adjusts its approach by generating multiple test patterns with different assumed error positions and iterating through them until successful decoding is achieved. This transforms the static bounded distance decoding into a dynamic, adaptive process that can handle variable numbers of errors.
Solution Approach 2:
The patent changes the parameter of error position assumptions by generating test patterns with different assumed error positions. Instead of using a fixed decoding approach, the system varies the parameter of which symbols are assumed to contain errors, allowing it to adapt to different error scenarios and overcome the limitation of fixed threshold-based decoding.
2Reliability
If the range of error symbol positions is expanded to handle more errors, then error correction capability improves, but calculation overhead increases
Solution Approach 1:
The patent applies partial action by testing a limited set of specific test patterns rather than exhaustively checking all possible error combinations. Instead of evaluating every possible error position scenario, the system selectively generates and tests a manageable number of patterns, achieving effective error correction without the computational burden of complete enumeration.
Solution Approach 2:
The patent uses preliminary action by pre-generating test patterns with assumed error positions before actual decoding is needed. The system prepares multiple candidate patterns in advance, which can be quickly evaluated during the decoding process, reducing the real-time computational load while maintaining comprehensive error correction capability.
Data Source
AI summary
A memory controller according to an embodiment includes a memory interface that reads out a received word from a non-volatile memory and a decoder that performs bounded distance decoding for the read received word. The decoder sets rm (rm is a natural number equal to or larger than 1) symbols of a plurality of symbols constituting the received word, as options of symbol positions at each of which an error is assumed, generates a test pattern in which m (m is a natural number equal to or larger than 1 and equal to or smaller than the rm) symbols of the rm symbols are objects of rewriting, generates test hard-decision values by rewriting each of hard-decision values of the m symbols that are objects of rewriting in the test pattern, among the symbols, and performs bounded distance decoding for the test hard-decision values.