Memory Controller Checkpointing Overhead Reduction
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Solution Overview
Problem
Current high reliability computer systems experience performance reduction due to checkpointing processes, which involve transferring and comparing CPU and memory data, leading to increased latency and overhead, especially when frequent data transfers are required.
Innovation Solution
Implementing a low latency checkpointing method where data is transferred and compared during normal operations, rather than during checkpoint operations, by modifying memory controllers to write changed data to both sides of mirrored memory and using inter-memory transfer interfaces to synchronize data between primary and secondary systems, thereby reducing the need for data transfer and comparison during checkpointing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent checkpointing is performed to maintain system reliability, then the second computer can take over execution with little impact to the user, but the system experiences performance reduction due to data transfer and comparison overhead
Solution Approach 1:
The patent applies preliminary action by transferring and comparing memory data during normal system operation rather than during checkpoint operations. The memory controllers continuously synchronize data between primary and secondary systems in the background, so when a checkpoint is needed, the data is already synchronized and no additional transfer or comparison time is required, thus maintaining both reliability and performance
Solution Approach 2:
The patent implements continuity of useful action by making data transfer and comparison ongoing processes that occur continuously during normal operation rather than as periodic interruptions. The memory controllers maintain continuous synchronization between primary and secondary memory systems, eliminating the need to stop execution for checkpoint operations while preserving system reliability
2Reliability
If data is transferred and compared during checkpoint operations, then system reliability is maintained, but increased latency and overhead occur
Solution Approach 1:
The patent applies preliminary action by completing data transfer and comparison before checkpoint operations are needed. Memory controllers continuously transfer data during normal operation and perform comparisons in the background, so when a checkpoint event occurs, synchronization is already complete and no additional time is lost
Solution Approach 2:
The patent uses memory controllers as intermediaries to handle data transfer and comparison tasks separately from the main execution path. The memory controllers continuously manage data synchronization between primary and secondary systems without requiring the CPU to stop or intervene, thus eliminating checkpointing overhead while maintaining reliability
3Productivity
If memory controllers write changed data to both sides of mirrored memory during normal operations, then data synchronization is achieved without checkpoint interruptions, but increased memory write operations occur
Solution Approach 1:
The patent applies local quality by having memory controllers selectively write only changed data to both sides of mirrored memory rather than writing all data. The system identifies which memory locations have been modified and performs targeted writes, reducing the overall energy consumption while maintaining synchronization efficiency
Data Source
AI summary
The disclosure describes a system including a first computer system including a first memory controller and a first inter-computer transfer interface to send information about write operations over an interconnect to a second computer system. A second computer system includes a second memory controller and a second inter-computer transfer interface to receive the information about the write operations over an interconnect, wherein the write operations are duplicated through the second memory controller. In other embodiments, a system includes a first computer system including a first memory controller and a first inter-computer transfer interface to send information about write operations of the first computer system during a lockstep operation. Still other embodiments are described.