Memory Controller Shortened LDPC Coding for Chip-Kill Recovery
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Solution Overview
Problem
Current memory systems, particularly SSDs using NAND-type flash memory, face challenges in efficiently correcting errors due to the limitations of existing error correction codes, which can lead to failures in decoding data, especially when dealing with variable degree nodes and parity bits.
Innovation Solution
A memory controller and method that construct a first code of data and parity bits, determine the number of distinct variable degree nodes, and create a shorter second code based on this information to improve decoding efficiency, allowing for successful decoding of failed word lines using a single LDPC chip-kill decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a first code with D data bits and P parity bits is used for decoding, then error correction capability is improved, but code length increases leading to larger system-on-chip area and higher power consumption
Solution Approach 1:
The patent changes the parameter of code length by constructing a shortened second code based on the number of distinct variable degree nodes L and data bits per node. This parameter change allows using a shorter code (second code) while maintaining error correction capability through the specific construction method that considers variable degree node distribution.
2Reliability
If multiple LDPC decoder hardware implementations are used to handle variable degree nodes, then decoding success rate is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent creates a universal shortened second code construction method that can handle variable degree nodes with a single decoder implementation. The code construction adapts to different variable degree node configurations (different L values and data bits per node) while maintaining a unified decoding approach, eliminating the need for multiple specialized decoders.
3Use of energy by stationary object
If a shorter second code is constructed based on variable degree nodes, then system-on-chip area and power consumption are reduced, but decoding complexity increases
Solution Approach 1:
The patent performs preliminary analysis of variable degree nodes during code construction, determining the number of distinct variable degree nodes L and the number of data bits per node before constructing the shortened code. This preliminary characterization simplifies the overall system by enabling a tailored shorter code that reduces power consumption while managing complexity through upfront planning.
Data Source
AI summary
Devices and methods that generate code on chip-kill parity in which the code is generated and shortened using variable node degree information for improved decoding of data. In one aspect, memory controller comprises an encoder configured to construct a first code of D data bits and P parity bits, determine the number of distinct variable degree nodes L and the number of data bits of each of the variable degree nodes in the first code, and construct a second code that is shorter than the first code based on the determined number of variable degree nodes and the number of data bits of each of the variable degree nodes in the first code.