Memory Controller Chip Select Training via Read Commands
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Solution Overview
Problem
Current methods for training chip select and clock signals in memory qualification and validation are cumbersome, error-prone, and time-consuming, especially as DRAM frequency increases, making it difficult to achieve skew compensation across the entire silicon process range.
Innovation Solution
A method and system for automatically training the skew between chip select and clock signals using read commands, which involves programming a memory controller, initializing a memory module, sending a read command to toggle the chip select state, counting data strobe signals, and determining the module's pass or error state to adjust delay values for proper timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual trace length extraction and software algorithm analysis are used for chip select training, then timing compensation can be achieved, but the process becomes cumbersome and error-prone
Solution Approach 1:
The memory controller automatically performs chip select training by sending read commands and counting data strobe signals without requiring external trace length extraction tools or manual software analysis. The system self-adjusts timing parameters through hardware-based automatic training sequences.
Solution Approach 2:
The patent replaces manual mechanical trace length extraction tools and software algorithms with an automated hardware-based training mechanism that uses read commands and data strobe counting to achieve timing compensation.
2Measurement precision
If manual tool setup and configuration are performed for each board type, then accurate timing analysis is possible, but the process becomes time-consuming
Solution Approach 1:
The memory controller autonomously performs timing analysis and training without requiring external tools or manual configuration for each board type. The automatic training sequence eliminates repetitive setup procedures while maintaining measurement accuracy.
Solution Approach 2:
The automated training mechanism works across different board types and memory configurations without requiring separate tool setups. A single universal training sequence handles various silicon process ranges and memory module types.
3Productivity
If DRAM frequency is increased to improve performance, then data throughput increases, but chip select and clock eye width decreases making skew compensation difficult
Solution Approach 1:
The training process uses feedback from counting data strobe signals to adjust chip select timing. The memory controller monitors the relationship between read commands and data strobe signals, using this feedback to automatically compensate for skew at higher frequencies.
Solution Approach 2:
The system performs automatic timing training and skew compensation before normal operation begins. By establishing correct timing relationships during initialization through read command sequences, the system prepares proper skew compensation for subsequent high-frequency operation.
Data Source
AI summary
A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.