Memory Controller Turbo-Decoding for Chipkill Bitline Recovery
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Solution Overview
Problem
Existing chipkill recovery schemes in memory systems, particularly in NAND flash memory, struggle with bitline failures due to the difficulty in recovering data when multiple memory chips fail, leading to increased data loss and reduced reliability.
Innovation Solution
Implementing a memory system with a memory controller that utilizes a chipkill parity scheme, involving turbo-decoding and feedback loops with adders to scale soft decode information, and using at least two decoders to enhance error correction capabilities, particularly for bitline errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chipkill recovery schemes are used, then data loss occurs during bitline failures, but implementing turbo-decoding with feedback loops and multiple decoders increases device complexity
Solution Approach 1:
The decoding process is segmented into multiple decoders (first decoder, second decoder, third decoder) that operate in a feedback loop. Each decoder handles specific aspects of the decoding process, dividing the complex error correction task into manageable segments that can be processed iteratively.
Solution Approach 2:
A feedback loop is implemented where the output of each decoder is fed back as input to subsequent decoders. The soft decode information from the first decoder is scaled and provided to the second decoder, which in turn provides information to the third decoder, creating an iterative feedback mechanism that progressively refines the error correction.
Solution Approach 3:
Scaling of soft decode information is performed as a preliminary action before subsequent decoding operations. The adders prior to each decoder scale the soft decode information from previous decoders, preparing optimized input data for the next decoding stage, which improves the overall effectiveness of the error correction process.
2Reliability
If turbo-decoding with scaling is implemented, then data recovery from bitline failures improves, but manufacturing complexity increases
Solution Approach 1:
The decoder structure is designed to be multi-functional, handling both initial decoding and iterative refinement in a unified architecture. The same decoder components are reused across multiple stages with different input configurations, reducing the need for entirely separate manufacturing processes for each decoding function.
Solution Approach 2:
The decoding architecture implements a nested structure where multiple decoders are arranged in a hierarchical feedback loop. The first decoder is nested within the overall system, which contains the second decoder, which in turn contains the third decoder, creating a nested arrangement that optimizes space and component utilization.
3Reliability
If multiple decoders in feedback loop are used, then error correction performance increases, but system resource consumption increases
Solution Approach 1:
The feedback loop mechanism allows for partial action where decoding can be stopped after a predetermined number of iterations if convergence is achieved. This prevents excessive energy consumption by avoiding unnecessary additional decoding cycles once the error correction has reached sufficient accuracy.
Solution Approach 2:
The decoding process operates in periodic cycles through the feedback loop, with each cycle consisting of sequential processing through the multiple decoders. This periodic structure allows for efficient resource management by organizing energy-intensive operations into regular, controllable intervals rather than continuous operation.
Data Source
AI summary
A memory system having a memory block and a memory controller in communication with the memory block. The memory controller is configured to: decode codewords in the memory block; determine failed codewords based on one or more parity checks including a chipkill parity; and turbo-decode the failed codewords using at least two decoders in a feedback loop with adders prior to each decoder for scaling soft decode information prior to subsequent decoding of the failed codewords.