Memory Controller Clock Domain Adaptation
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Solution Overview
Problem
Memory controllers face challenges in accommodating frequency changes in processor cores, leading to buffer overflow or underflow issues due to mismatched clock frequencies between processor and memory domains, which affects data transfer efficiency and power management.
Innovation Solution
Implementing asynchronous read and write buffers with data flow logic that stalls processing and adjusts command issuance rates in response to frequency changes, ensuring data is transferred only when available and at rates that prevent buffer overflow or underflow, using a system with a constant memory clock and variable processor clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the processor frequency is reduced to conserve power, then power consumption is reduced, but the read buffer may overflow because read data is received at a rate greater than the processor can read it
Solution Approach 1:
The memory controller dynamically adjusts the data transfer rate from the read buffer to the processor based on the processor's current clock frequency. When the processor frequency changes, the memory controller modifies the read command issuance rate to match the processor's capabilities, preventing buffer overflow while maintaining efficient power management.
Solution Approach 2:
The system implements feedback mechanisms where the memory controller monitors the processor's clock frequency and adjusts data transfer rates accordingly. This feedback loop ensures that read data is transferred at a rate compatible with the processor's current operating speed, preventing buffer overflow when frequency is reduced for power conservation.
2Use of energy by moving object
If the processor frequency is reduced to conserve power, then power consumption is reduced, but the write buffer may under run because write data is transferred at a slower rate than timing requirements allow
Solution Approach 1:
The memory controller dynamically adjusts write operation timing based on the processor's clock frequency. When frequency is reduced, the controller modifies write command issuance and data transfer timing to ensure that write buffers are filled at appropriate rates, preventing underflow while maintaining power efficiency.
Solution Approach 2:
The system uses feedback from the processor's clock frequency to adjust write buffer management. The memory controller monitors frequency changes and modifies write operation timing accordingly, ensuring data is written to buffers at rates that satisfy timing requirements even when processor frequency is reduced for power conservation.
3Productivity
If the memory controller uses large command queues to receive commands from the processor, then command processing capacity is increased, but the complexity of coordinating between different clock domains increases
Solution Approach 1:
The memory controller segments command processing into distinct queues: a command queue in the processor clock domain for receiving commands, and a separate memory interface sequencer in the memory clock domain for executing memory operations. This segmentation allows each component to operate at its optimal frequency while maintaining clear responsibilities and reducing coordination complexity.
Solution Approach 2:
The memory controller acts as an intermediary between the processor and memory, using command queues and sequencers to bridge the frequency difference between clock domains. This intermediary structure absorbs the complexity of frequency coordination while presenting simplified interfaces to both the processor and memory subsystems.
Data Source
AI summary
The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.