Memory Controller Clock Frequency Dynamics
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Solution Overview
Problem
Rewritable non-volatile memory modules face challenges in balancing operation speed and error probability due to varying clock signal frequencies, leading to either increased errors at higher speeds or reduced performance at lower speeds.
Innovation Solution
A memory controlling method and circuit unit that provide distinct clock signals for reading and writing operations, allowing for increased operation speed while minimizing error probabilities by adjusting frequencies based on specific operations and data importance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the clock signal is increased to improve operation speed, then the operation speed of the rewritable non-volatile memory module is improved, but the probability of having errors for some operations is increased
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable rather than fixed. The memory controlling circuit unit dynamically changes the clock signal frequency based on the operation type (read or write), allowing the system to adapt between speed and reliability requirements for different operations
Solution Approach 2:
The patent changes the parameter of clock signal frequency based on operation type. Specifically, a first clock signal frequency is used for read operations and a second clock signal frequency (different from the first) is used for write operations, optimizing both speed and reliability for each operation type
2Reliability
If the frequency of the clock signal is decreased to reduce error probability, then the probability of having errors for some operations is decreased, but the operation speed of the rewritable non-volatile memory module is reduced
Solution Approach 1:
The system dynamically adjusts clock signal frequency based on operation requirements. For write operations where reliability is critical, a lower frequency (second clock signal) is used to reduce error probability, while for read operations where speed is prioritized, a higher frequency (first clock signal) is used
Solution Approach 2:
The patent changes the clock signal frequency parameter according to operation type. By using a second frequency for write operations that differs from the first frequency used for read operations, the system optimizes reliability for data writing while maintaining speed for data reading
Data Source
AI summary
A memory controlling method, a memory storage device and a memory controlling circuit unit are provided. The method includes: providing a first clock signal to a rewritable non-volatile memory module and reading a first data in the rewritable non-volatile memory module according to the first clock signal; providing a second clock signal to the rewritable non-volatile memory module and writing a second data into the rewritable non-volatile memory module according to the second clock signal. A frequency of the second clock signal is different from a frequency of the first clock signal. Accordingly, an operation speed of the rewritable non-volatile memory module may be increased and probabilities of having errors for some operations are decreased.