Memory Controller Mapping CNN Activations
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Solution Overview
Problem
Existing technologies fail to provide an optimized way for accessing and storing vector element values in memory for high-speed read and write processes without the need for masking or de-masking specific bit areas in consecutive memory words, which is crucial for real-time applications of convolutional neural networks (CNNs).
Innovation Solution
A memory controller circuit and method that allow for flexible mapping of pixel values of a convolutional neural network to physical memory words using various mapping schemas, such as intra-word adjacent mapping, kernel word interleaving, and activation word interleaving, depending on a selection parameter value. This enables optimal alignment and storage of variables with memory word boundaries, balancing memory usage and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If row-wise reading and column-wise storage of activation values is used in CNN matrix multiplications, then memory addressing flexibility is improved, but computing speed and performance deteriorate due to inefficient memory access patterns
Solution Approach 1:
The patent implements dynamic mapping schemas that can be selected based on operational requirements. The memory controller circuit switches between different mapping schemas (e.g., row-major, column-major, interleaved) to optimize for either flexibility or speed depending on the specific CNN operation being performed, making the system adaptive rather than static.
Solution Approach 2:
The invention changes the parameter of memory mapping organization by providing multiple mapping schemas with different data arrangement strategies. By altering how activation values are mapped to memory words (e.g., changing from standard row-major to specialized interleaved mappings), the system optimizes memory access patterns for high-speed computing without sacrificing addressing flexibility.
2Ease of manufacture
If standard memory mapping is used for CNN activations, then implementation simplicity is improved, but real-time processing capability deteriorates due to insufficient optimization for high-speed read/write operations
Solution Approach 1:
The patent segments the memory mapping approach into multiple specialized schemas, each optimized for specific access patterns in CNN operations. Instead of using a single general-purpose mapping, the system divides the solution into specialized mappings (e.g., for row-wise reads, column-wise writes, or interleaved access), making real-time processing reliable while keeping each individual schema relatively simple.
Solution Approach 2:
The memory controller circuit is designed with multi-functionality to support multiple mapping schemas within a single unified architecture. This universal design allows the same hardware to adapt to different CNN layer requirements and access patterns, ensuring real-time processing capability without requiring separate specialized hardware for each operation type.
3Manufacturing precision
If masking or de-masking of specific bit areas in consecutive memory words is used, then data storage precision is improved, but processing complexity and time consumption increase
Solution Approach 1:
The patent applies preliminary action by pre-organizing data according to specialized mapping schemas before processing. Activation values are mapped to memory words in advance using optimized patterns that inherently maintain precision without requiring subsequent masking or de-masking operations during processing, thereby eliminating time-consuming bit manipulation steps.
Solution Approach 2:
The invention extracts the precision-maintenance function from the processing pipeline by incorporating it into the initial mapping stage. Instead of needing to mask/de-mask bits during computation, the specialized mappings ensure proper data alignment and precision are established upfront, removing the harmful masking operations from the critical processing path.
Data Source
AI summary
A memory controller circuit for mapping data of a convolutional neural network to a physical memory is disclosed. The memory controller circuit comprises a receiving unit to receive a selection parameter value, and a mapping unit to map pixel values of one layer of the convolutional neural network to memory words of the physical memory according to one of a plurality of mapping schemas, wherein the mapping is dependent on the value of the received selection parameter value.