Memory Controller Coalescing Parallel Requests
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Solution Overview
Problem
General Purpose Graphics Processing Units (GPGPUs) with a large number of computation units face inefficiencies in servicing memory requests due to limited memory access sizes and performance penalties when accessing non-contiguous DRAM addresses, leading to suboptimal memory transfer efficiency.
Innovation Solution
A multiprocessor system that executes parallel threads and performs a coalesce check to coalesce memory requests from proximate memory addresses on a common memory page, using a memory controller to issue simultaneous memory requests and optimize memory transfer efficiency by grouping requests into contiguous regions, thereby reducing the number of memory accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If memory requests are issued individually by each computation unit, then each request can be processed independently, but memory transfer efficiency deteriorates due to limited access sizes and non-contiguous addressing
Solution Approach 1:
The patent merges multiple individual memory requests from different computation units into a single coalesced memory request when the requested addresses are proximate and lie within the same memory page. This combining operation maintains the independence of individual requests while achieving efficient bulk processing through the memory controller's coalescing logic, thereby resolving the contradiction between independent processing and transfer efficiency.
2Device complexity
If memory access size is limited to fixed sizes, then memory controller design is simplified, but memory transfer efficiency deteriorates when individual computation units require smaller access sizes
Solution Approach 1:
The patent segments the memory address space into memory pages and further segments memory requests into coalesce groups based on address proximity within pages. This segmentation allows the memory controller to handle fixed-size efficient accesses at the page level while accommodating variable-sized individual computation unit requests through the segmentation of request groups, resolving the contradiction between simplified controller design and transfer efficiency.
3Adaptability or versatility
If memory requests access non-contiguous DRAM addresses, then flexibility in data access is improved, but performance deteriorates due to page switch penalties
Solution Approach 1:
The patent applies local quality by treating memory requests differently based on their address characteristics: requests with proximate addresses within the same page are coalesced for efficient contiguous access, while requests to non-contiguous addresses are handled separately. This localized optimization maintains access flexibility for diverse addressing patterns while achieving high performance for contiguous accesses, resolving the contradiction between flexibility and performance.
Data Source
AI summary
A multiprocessor system executes parallel threads. A controller receives memory requests from the parallel threads and coalesces the memory requests to improve memory transfer efficiency.