Memory Controller Wear Leveling via Cold Data Classification

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing memory devices face challenges in maintaining operational reliability and efficient wear leveling due to uneven program/erase operations across memory regions, leading to reduced lifespan and performance.

Innovation Solution

A memory controller that includes a request receiving circuit, a data characteristic storage circuit, and a wear leveling control circuit, which maintains a cold data list to prioritize data output and manage wear leveling based on data characteristics, ensuring that data marked as cold is preferentially flushed and regions are evenly utilized.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If data is written to memory regions in FIFO order, then write simplicity is maintained, but program/erase operations become uneven across regions leading to reduced lifespan

Engineering Contradiction:
Improvewrite simplicityVSAvoidoperational reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The memory controller preliminarily classifies incoming data as hot or cold before writing to memory regions. Cold data is marked with a cold data indicator and written to specific regions, while hot data is written to other regions. This preliminary classification ensures balanced program/erase operations across all memory regions, extending memory device lifespan while maintaining simple FIFO write operations.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If all data is treated equally during wear leveling, then control simplicity is maintained, but cold data remains in memory longer than necessary reducing efficiency

Engineering Contradiction:
Improvecontrol simplicityVSAvoiddata flush efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The wear leveling controller applies different handling rules to different data types within the same memory system. Cold data (marked with cold data indicator) is preferentially selected for flushing to external storage, while hot data is retained in memory. This local quality differentiation enables efficient cold data flush operations without significantly increasing control complexity, as the controller only needs to check the cold data indicator flag.

Inventive Principle:
Principle #3Local quality

3Device complexity

If cold data is not identified and separated, then memory management simplicity is maintained, but wear leveling performance deteriorates due to uneven program/erase operations

Engineering Contradiction:
Improvememory management simplicityVSAvoidwear leveling performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The system performs preliminary classification of data as hot or cold at the time of write operation, marking cold data with a cold data indicator. This preliminary action enables the wear leveling controller to efficiently identify and manage cold data without complex real-time analysis, maintaining simple memory management while significantly improving wear leveling performance through balanced program/erase operations across memory regions.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11126370B2Memory controller and operating method thereof
Publication Date: 2021.09.21 MIMIRIP LLC
  • US11126370B2 patent drawing
  • US11126370B2 patent drawing
  • US11126370B2 patent drawing

AI summary

A memory controller for controlling an operation of a memory device includes a request receiving circuit and a data characteristic storage circuit. The request receiving circuit receives from a host a flush request and a logical address corresponding to the flush request, and generates a control signal in response to the received flush request. The data characteristic storage circuit stores a cold data list, and updates the cold data list in response to the control signal from the request receiving circuit.