Memory Controller Architecture with Color Pipelines
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Solution Overview
Problem
Conventional memory interface circuitry on programmable integrated circuits either lacks scheduling efficiency for memory bandwidth utilization or is limited in flexibility when scaling across different memory protocols and topologies, with hardened solutions offering high performance but limited scalability and soft solutions providing flexibility but reduced performance.
Innovation Solution
The implementation of a memory controller architecture that partitions memory controller circuitry into memory protocol agnostic blocks, memory protocol dependent blocks, and user-dependent blocks, using multiple color pipelines for parallel processing of memory access requests, a rate matching circuit for clock domain crossing, and a coloring control circuit for even distribution of memory commands across pipelines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardened/fixed application-specific memory interface solutions are used, then operating frequency and performance are improved, but scalability across different memory protocols and topologies deteriorates
Solution Approach 1:
The memory interface is segmented into separate modules: a configurable memory controller that handles protocol-specific logic and a hardened interface layer that provides high-performance memory access. This segmentation allows the controller to be adapted to different protocols while maintaining high-speed access through the hardened interface.
Solution Approach 2:
The memory controller incorporates dynamic configuration capabilities that allow it to be reprogrammed or reconfigured for different memory protocols and topologies. This dynamic adaptability enables the same hardware platform to support multiple memory standards while maintaining optimized performance characteristics.
2Adaptability or versatility
If soft/programmable memory interface solutions are used, then flexibility for different memory protocols is improved, but scheduling efficiency and performance deteriorate
Solution Approach 1:
The architecture separates the programmable memory controller from the performance-critical memory access paths. The controller can be softly programmed for protocol flexibility, while the interface layer maintains hardened, efficient scheduling and access patterns, thus preserving both adaptability and performance.
Solution Approach 2:
A dedicated memory interface layer acts as an intermediary between the programmable controller and the physical memory. This intermediary handles the time-critical scheduling and access optimization, allowing the programmable controller to focus on protocol adaptation without compromising scheduling efficiency.
3Productivity
If out-of-order memory controllers are used, then memory bandwidth utilization is improved, but scheduling determinism deteriorates
Solution Approach 1:
The memory controller implements dynamic scheduling that can adapt its behavior based on system conditions. It can switch between in-order and out-of-order processing modes, or use priority-based arbitration, allowing it to maintain determinism when needed while optimizing bandwidth when conditions permit non-deterministic scheduling.
Solution Approach 2:
The controller allows configuration of scheduling parameters and arbitration policies that can be adjusted to balance between determinism and bandwidth utilization. By changing these parameters, the system can optimize for either deterministic timing or maximum throughput depending on the application requirements.
Data Source
AI summary
Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in a third clock domain that is an integer multiple of the second clock domain. The user logic interface may include only user-dependent blocks. The physical layer interface may include memory protocol agnostic blocks and/or memory protocol specific blocks. The memory controller may include both memory protocol agnostic blocks and memory protocol dependent blocks. The memory controller may include one or more color pipelines for scheduling memory requests in a parallel arbitration scheme.