Memory Controller Command Address Signal Power Optimization
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Solution Overview
Problem
As memory devices advance to higher generations like LPDDR5, LPDDR6, and LPDDR7, the power consumption of memory systems increases, particularly when generating command address signals with a higher number of bits at a low logic level.
Innovation Solution
A memory system that includes a memory controller configured to generate a command address signal using a command address bus inversion (CABI) operation and parity calculation. The memory controller sets the CABI to a high logic level when the number of data bits at a low logic level is greater than or equal to (n/2)−1, where n is the total number of bits in the command address signal, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of bits at a low logic level is increased in the command address signal, then the memory system can represent more address combinations, but the power consumption increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the logic level distribution of command address signal bits based on the actual address requirements. Instead of using a fixed pattern with many low logic level bits, the system calculates the optimal number of low logic level bits as (n/2)-1 and adjusts the signal accordingly, changing the parameter of logic level distribution to balance address representation capability with power consumption.
Solution Approach 2:
The system implements dynamics by making the command address signal generation adaptive rather than static. The memory controller dynamically determines the number of low logic level bits based on the current address decoding requirements and adjusts the signal in real-time. This dynamic adjustment allows the system to optimize power consumption while maintaining the necessary address representation capability for different memory operations.
2Use of energy by moving object
If the number of bits at a high logic level is increased, then the power consumption is reduced, but the address representation capability is limited
Solution Approach 1:
The patent changes the parameter of logic level distribution by calculating the optimal balance point. Instead of maximizing high logic level bits to minimize power consumption, the system sets the number of low logic level bits to (n/2)-1, which implies a specific distribution of high and low logic level bits. This parameter change achieves a balance between power savings and address representation capability.
Solution Approach 2:
The system applies partial action by using a controlled number of low logic level bits rather than minimizing them to zero. By setting the number of low logic level bits to (n/2)-1, the system uses a partial amount of low logic level bits necessary for proper address decoding, avoiding both excessive low logic level bits (which would waste power) and insufficient low logic level bits (which would limit address representation).
Data Source
AI summary
A memory controller generates a command address signal (CAS), and includes a first bit signal generator (BSG) configured to generate a data signal (DS) as a plurality of data bits, a second BSG configured to generate a command address bus inversion bit (CABIB) having a logic level that is a function of a number of data bits within the DS having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the DS and the CABIB having a high level is an even number. The CABIB is set to a high logic level when “n”, which is a number of bits included in the CAS, is a positive integer greater than one, and a number of data bits within the DS having a low level is greater than or equal to (n/2)−1.