Memory Controller Command Alignment for Low-Frequency Operation
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Solution Overview
Problem
Existing memory controllers operating at half the frequency of a DRAM memory clock face delays due to the generation of NOP commands, limiting the ability to issue multiple commands consecutively and reducing efficiency compared to controllers operating at the same frequency as the DRAM clock.
Innovation Solution
A memory controlling device that includes a request generating section, row and column selecting information retaining sections, a command generating section, and a command aligning section, allowing for the generation and alignment of multiple commands at a frequency lower than the DRAM clock, enabling efficient issuance of commands by managing memory bank operations and aligning commands with the DRAM clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a memory controller operates at 1/2N of the frequency of the memory clock to generate commands, then the memory controller can operate at a lower frequency, but NOP commands are generated in the first or second phase of the two-phase control signal, causing delays in command issuance
Solution Approach 1:
The command generating section is divided into multiple generating units (first command generating section, second command generating section, etc.) that operate in parallel. Each unit generates commands independently at 1/2N frequency, and multiple commands are issued simultaneously to different memory banks, eliminating the need for NOP commands and resolving the time delay while maintaining low operating frequency
Solution Approach 2:
The patent transitions from sequential command generation (single phase) to parallel command generation (multiple phases/dimensions). By issuing 2N phases of control signals and converting them to 1 phase in the memory interface circuit, the system can generate multiple commands concurrently at lower frequency without introducing NOP delays
2Productivity
If a memory controller operates at the same frequency as the memory clock to generate commands, then commands can be issued without delay, but the memory controller cannot operate at a lower frequency than the memory clock
Solution Approach 1:
The command generating section uses multiple parallel generating units that each operate at 1/2N frequency. By segmenting the command generation into multiple independent units working simultaneously, the system achieves high command issuance efficiency equivalent to operating at full frequency while the controller itself operates at lower frequency
Solution Approach 2:
The patent changes the operational parameters by introducing 2N phases of control signals operating at 1/2N frequency and converting them to 1 phase for memory interface. This parameter transformation allows the controller to maintain high productivity while operating at reduced frequency
Data Source
AI summary
A memory controlling device that includes a request generating section for generating a memory request, a row selecting information retaining section that retains data relative to row address information, a column selecting information retaining section that retains data relative to column address information, a memory bank information for managing section operation states of the memory device, a command generating section for generating operation commands, and a command aligning section that synchronizes the operation commands with the clock.