Memory Controller Command Mapping for Data Bandwidth Efficiency
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Solution Overview
Problem
Memory controllers face inefficiencies in data bandwidth utilization due to wide burst lengths, leading to breaks in data streams when maintenance commands are executed, resulting in up to 25% loss in data bus bandwidth efficiency, especially with small burst lengths and wide data interfaces.
Innovation Solution
Implementing a method where two read or write data requests are executed in separate clock cycles, allowing maintenance commands to be executed concurrently, thereby maintaining a continuous data stream without breaks, and utilizing a command mapping scheme that repurposes row-activate command pins to send additional column addresses, enabling dual column commands in a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wide burst lengths are used in memory devices, then command bandwidth is improved, but data bandwidth efficiency deteriorates due to unneeded data transfers and breaks in data streams
Solution Approach 1:
The patent segments the command execution process by implementing separate command execution paths for data commands and maintenance commands. Data commands execute in a first path while maintenance commands execute in a second path, allowing independent optimization of each command type and preventing maintenance commands from breaking data streams.
Solution Approach 2:
The patent implements dynamic command mapping where the memory controller can flexibly route different command types to different execution paths based on real-time needs. This dynamic routing allows the system to adapt command execution to maximize data bandwidth efficiency while maintaining necessary command bandwidth for maintenance operations.
2Productivity
If maintenance commands are executed during data transfer, then command bandwidth utilization is improved, but data stream continuity deteriorates
Solution Approach 1:
The patent divides command execution into separate segments: a first execution path for data commands and a second execution path for maintenance commands. This segmentation ensures that maintenance commands cannot interrupt data streams, maintaining continuity while still allowing maintenance operations to execute concurrently in the background.
Solution Approach 2:
The patent introduces an intermediary command mapping mechanism that mediates between data commands and maintenance commands. This intermediary layer routes maintenance commands through a separate path while allowing them to coordinate with data command execution, preventing interruptions to the data stream.
3Device complexity
If command mapping scheme is simplified, then device complexity is reduced, but pin count increases to maintain functionality
Solution Approach 1:
The patent implements a universal command mapping scheme where the same command bus and data bus infrastructure handles both data commands and maintenance commands through different execution paths. This multi-functional approach maintains functionality without requiring separate physical interfaces, avoiding pin count increases while reducing command mapping complexity.
Data Source
AI summary
An exemplary system of the present disclosure comprises a memory controller, a command bus, a data bus, a memory device and a memory. The memory device is coupled to the memory controller by the command bus and the data bus. The memory stores instructions that when executed by the computer system perform a method of requesting data from the memory device. This method comprises receiving a plurality of commands for the memory device from the command bus, the memory device clocked by a clock. At least one command of the plurality of commands includes a first command and a second command within a single clock cycle of said clock. At least one of the first command and second command is a data access command. The first command is executed during a first clock cycle and the second command is executed during a second subsequent clock cycle.