Memory Controller Command Mixing to Reduce tCCD Delays
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Solution Overview
Problem
The inefficiency in memory devices arises from the mismatch between command transfer times exceeding data transfer times, leading to disruptions in performance as the number of input/output pads decreases with increased capacity.
Innovation Solution
A memory system with a memory controller that operates in two modes: a first mode for continuous command transfer and a second mode for mixing commands, allowing for adjusted command latch timing based on flag information, thereby reducing CAS-to-CAS delay time (tCCD) and preventing data transfer gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of input/output pads is decreased to reduce device size, then the memory capacity can be increased, but the command transfer time exceeds the data transfer time causing performance disruption
Solution Approach 1:
The patent implements dynamic operation modes (first mode and second mode) that allow the memory device to adapt its command transfer characteristics. In the second mode, the device mixes commands with data transfers, dynamically adjusting the command transfer approach to match data transfer timing requirements, thereby resolving the time mismatch problem while maintaining high capacity
Solution Approach 2:
The patent changes operational parameters by introducing mode register information that controls different transfer modes. The system can switch between continuous command transfer (first mode) and mixed command-data transfer (second mode), adjusting timing parameters like tCCD to optimize the balance between command and data transfer times
2Quantity of substance
If commands are transferred over multiple clock cycles to accommodate increased address bits, then memory capacity can be increased, but the command transfer time becomes longer than data transfer time
Solution Approach 1:
The patent merges command transfer with data transfer operations in the second mode. By mixing commands with data transfers and inserting commands between data transfers, the system combines previously separate operations into a unified transfer sequence, improving overall productivity by eliminating idle time and ensuring continuous bus utilization
Solution Approach 2:
The patent ensures continuous useful action by preventing gaps in data transfer. The mixed mode operation inserts commands between data transfers rather than allowing idle periods, maintaining continuous utilization of the data bus and maximizing transfer efficiency throughout the operation
3Productivity
If the command latch timing is adjusted to match data transfer time, then transfer efficiency can be improved, but the command transfer sequence becomes more complex
Solution Approach 1:
The patent uses dynamic timing adjustment where the memory device can switch between different latch timing modes. The command latch timing is adapted based on the operation mode, with the device dynamically adjusting when to latch commands relative to data transfers, optimizing timing without requiring complex fixed timing circuits
Data Source
AI summary
A memory system, including a memory controller and a memory, wherein the memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller mixes a second command with the first command and transmits the mixture of the first command and the second command. The memory changes command latch timing depends on the first or second mode.