Memory Controller Command Queue Entry Merging for Throughput

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Solution Overview

Problem

Conventional memory controllers face inefficiencies when processing a series of short memory transactions due to limited command queue depth, leading to reduced throughput and inability to accept additional transactions, especially when host memory port bandwidth exceeds memory interface bursts.

Innovation Solution

Implementing a command queue with entry merging capabilities, where multiple short transactions with contiguous or same memory page access ranges are merged into single transactions, reducing the number of queue entries required and optimizing memory access efficiency without increasing queue depth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the command queue depth is increased to process more short memory transactions, then the throughput is improved, but the memory space occupation and circuitry complexity increase

Engineering Contradiction:
ImprovethroughputVSAvoidmemory space occupation
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent merges multiple short memory transactions that access the same memory page into a single combined transaction. This is achieved by detecting when multiple transactions target the same page, consolidating them into one transaction with aggregated data, and issuing it as a single command to the memory device. This merging approach reduces the number of queue entries needed while maintaining high throughput for processing short transactions.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If the command queue depth is increased to accept more outstanding transactions, then the ability to handle burst traffic is improved, but the circuitry complexity and cost increase

Engineering Contradiction:
Improveability to accept additional transactionsVSAvoidcircuitry
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines multiple transactions into single merged transactions, which reduces the number of queue entries required. This allows the system to handle burst traffic and accept more outstanding transactions without proportionally increasing queue depth, thereby reducing circuitry complexity and cost while maintaining adaptability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The command queue structure is made dynamic by allowing entries to be merged and consolidated based on real-time transaction patterns. When short transactions are detected targeting the same page, the system dynamically merges them, effectively adapting the queue's processing capacity without requiring a fixed increase in queue depth or circuitry.

Inventive Principle:
Principle #15Dynamics

3Reliability

If multiple short transactions are processed individually, then transaction processing accuracy is maintained, but the command queue efficiency decreases

Engineering Contradiction:
Improvetransaction processing accuracyVSAvoidcommand queue efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges multiple short transactions into single combined transactions while preserving the integrity and accuracy of each individual transaction's data access requirements. The merging process carefully aggregates data from multiple transactions and ensures that the combined transaction maintains the correct memory access patterns, thereby maintaining processing accuracy while improving command queue efficiency through reduced entry usage.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10579303B1Memory controller having command queue with entries merging
Publication Date: 2020.03.03 CADENCE DESIGN SYST INC
  • US10579303B1 patent drawing
  • US10579303B1 patent drawing
  • US10579303B1 patent drawing

AI summary

Aspects of the present disclosure involve an apparatus including a port interface coupled with a data bus to receive memory transaction commands, and a command queue coupled with the port interface. Additional aspects include methods of operating such an apparatus, and electronic design automation (EDA) devices to generate design files associated with such an apparatus. The command queue includes a plurality of memory entries to store memory transaction commands, a placement logic module to combine a received memory transaction command with a memory transaction command previously stored in one of the plurality of memory entries of the command queue, and a selection logic module to determine an order to transmit memory transaction commands stored in the plurality of memory entries and transmit the stored memory transaction commands according to the determined order to a memory interface.